SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes USB module integration in the device, including information about clocks, resets, and hardware requests.
Figure 12-1921 show the integration of the USB subsystem in the device.
For Superspeed SerDes integration details, please refer to in Serializer/Deserializer (SerDes).
Table 12-3800 through Table 12-3802 summarize the integration of USBSS.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
USB3SS0 | PSC0 | PD0 | LPSC20 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
USB3SS0 | ACLK | MAIN_SYSCLK0 | PLL_CTRL0 | VBUSM interface clock |
PCLK | MAIN_SYSCLK0/4 | PLL_CTRL0 | VBUSP interface clock | |
BUFCLK | MAIN_SYSCLK0/2 | PLL_CTRL0 | VBUSM bridge clock | |
CLK_LPM | MAIN_PLL1_HSDIV7_CLKOUT | MAIN_PLL1 | Low power clock (24 MHz). This clock has to be free running when USB is enabled. | |
USB2PHY0 | USB2_REFCLOCK | WKUP_HFOSC0_CLK | WKUP_HFOSC0 | USB2PHY reference clock. HFOSC selected via CTRLMMR_USB0_CLKSEL. Frequency value must be indicated to PHY via USB3P0SS_STATIC_CONFIG. |
HFOSC1_CLK | HFOSC1 | |||
USB2_APB_PCLK | MAIN_SYSCLK0/4 | PLL_CTRL0 | USB2PHY VBUSP interface clock | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
USB3SS0 | USB0_RST | MOD_G_RST | LPSC20 | USB3SS0 hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt | Destination Interrupt Input | Destination | Description | Type |
USB3SS0 | IRQ_[0:7] | GIC500_SPI_IN_[128:135] | COMPUTE_CLUSTER0 | 8 event ring interrupts in host mode. In device mode, IRQ[6] is device USB interrupt and IRQ[7] is device wakeup request. | Level |
MAIN2MCU_LVL_INTRTR0_IN_[128:135] | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_[281:288] | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_[281:288] | R5FSS0_CORE1 | ||||
HOST_SYSTEM_ERROR | GIC500_SPI_IN_782 | COMPUTE_CLUSTER0 | USB host system error | Level | |
MAIN2MCU_LVL_INTRTR0_IN_157 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_361 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_361 | R5FSS0_CORE1 | ||||
OTGIRQ | GIC500_SPI_IN_152 | COMPUTE_CLUSTER0 | USB OTG events | Level | |
MAIN2MCU_LVL_INTRTR0_IN_152 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_280 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_280 | R5FSS0_CORE1 | ||||
ASF_INT_NONFATAL | ESM0_LVL_IN_124 | ESM0 | USB safety features nonfatal interrupt | Level | |
ASF_INT_FATAL | ESM0_LVL_IN_125 | ESM0 | USB safety features fatal interrupt | Level | |
A_ECC_AGGR_CORRECTED_ERR_LEVEL | ESM0_LVL_IN_126 | ESM0 | ECC aggregator interrupt | Level | |
A_ECC_AGGR_UNCORRECTED_ERR_LEVEL | ESM0_LVL_IN_127 | ESM0 | ECC aggregator interrupt | Level | |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
USB3SS0 | - | - | - | No PDMA channels to external DMA engines. USB has an internal DMA controller. | - |