SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-4404 lists the memory-mapped registers for the MMCSD0 RX RAM ECC Aggregator. All register offset addresses not listed in Table 12-4404 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4000h |
Offset | Acronym | Register Name | MMCSD0_ECC_AGGR_RXMEM Physical Address |
---|---|---|---|
0h | MMCSD0_RXECC_REV | Aggregator Revision Register | 02A2 4000h |
8h | MMCSD0_RXECC_VECTOR | ECC Vector Register | 02A2 4008h |
Ch | MMCSD0_RXECC_STAT | Misc Status Register | 02A2 400Ch |
3Ch | MMCSD0_RXECC_SEC_EOI_REG | SEC EOI Register | 02A2 403Ch |
40h | MMCSD0_RXECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A2 4040h |
80h | MMCSD0_RXECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A2 4080h |
C0h | MMCSD0_RXECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A2 40C0h |
13Ch | MMCSD0_RXECC_DED_EOI_REG | DED EOI Register | 02A2 413Ch |
140h | MMCSD0_RXECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A2 4140h |
180h | MMCSD0_RXECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A2 4180h |
1C0h | MMCSD0_RXECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A2 41C0h |
200h | MMCSD0_RXECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A2 4200h |
204h | MMCSD0_RXECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A2 4204h |
208h | MMCSD0_RXECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A2 4208h |
20Ch | MMCSD0_RXECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A2 420Ch |
MMCSD0_RXECC_REV is shown in Figure 12-2285 and described in Table 12-4406.
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Aggregator Revision Register
Revision parameters.
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL Version |
10-8 | REVMAJ | R | 2h | Major Version |
7-6 | CUSTOM | R | 0h | Custom Version |
5-0 | REVMIN | R | 0h | Minor Version |
MMCSD0_RXECC_VECTOR is shown in Figure 12-2286 and described in Table 12-4408.
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ECC Vector Register
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Read Done Status to indicate if read on the serial ECC interface is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read Address |
15 | RD_SVBUS | R/W1S | 0h | Read Trigger Write 1h to trigger a read on the serial ECC interface. |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | ECC RAM ID Value written to select the corresponding ECC RAM for control or status. |
MMCSD0_RXECC_STAT is shown in Figure 12-2287 and described in Table 12-4410.
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Misc Status Register
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 400Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-1h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 1h | Indicates the number of RAMs serviced by the ECC aggregator. |
MMCSD0_RXECC_SEC_EOI_REG is shown in Figure 12-2288 and described in Table 12-4412.
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SEC EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 403Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | SEC EOI |
MMCSD0_RXECC_SEC_STATUS_REG0 is shown in Figure 12-2289 and described in Table 12-4414.
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SEC Interrupt Status Register 0
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_PEND | R/W1S | 0h | Interrupt Pending Status for rxmem_pend |
MMCSD0_RXECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-2290 and described in Table 12-4416.
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SEC Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for rxmem_pend |
MMCSD0_RXECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-2291 and described in Table 12-4418.
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SEC Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 40C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for rxmem_pend |
MMCSD0_RXECC_DED_EOI_REG is shown in Figure 12-2292 and described in Table 12-4420.
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DED EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 413Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | DED EOI |
MMCSD0_RXECC_DED_STATUS_REG0 is shown in Figure 12-2293 and described in Table 12-4422.
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DED Interrupt Status Register 0
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_PEND | R/W1S | 0h | Interrupt Pending Status for rxmem_pend |
MMCSD0_RXECC_DED_ENABLE_SET_REG0 is shown in Figure 12-2294 and described in Table 12-4424.
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DED Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for rxmem_pend |
MMCSD0_RXECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-2295 and described in Table 12-4426.
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DED Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 41C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for rxmem_pend |
MMCSD0_RXECC_AGGR_ENABLE_SET is shown in Figure 12-2296 and described in Table 12-4428.
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Aggregator Interrupt Enable Set Register
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for serial ECC interface timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
MMCSD0_RXECC_AGGR_ENABLE_CLR is shown in Figure 12-2297 and described in Table 12-4430.
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Aggregator Interrupt Enable Clear Register
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for serial ECC interface timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
MMCSD0_RXECC_AGGR_STATUS_SET is shown in Figure 12-2298 and described in Table 12-4432.
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Aggregator Interrupt Status Set Register
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 4208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for serial ECC interface timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
MMCSD0_RXECC_AGGR_STATUS_CLR is shown in Figure 12-2299 and described in Table 12-4434.
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Aggregator Interrupt Status Clear Register
Instance | Physical Address |
---|---|
MMCSD0_ECC_AGGR_RXMEM | 02A2 420Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for serial ECC interface timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |