SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 12-1952 shows the I/O interface signals of SERDES.
Although containing some of the basic external components, Figure 12-1952 must not be considered as an exhaustive guide for the PCB designer. TI provides additional documents for those who are willing to design PCBs and/or fine tune the SerDes.
Table 12-3869 describes the external signals of SERDES0 module.
Device Pin | Module Signal | I/O(1) | Description | Value at Reset |
---|---|---|---|---|
SERDES0_RX0_P | RX_P_LN0 | I | SerDes differential data receive pins. Lane 0 | HiZ |
SERDES0_RX0_N | RX_M_LN0 | I | HiZ | |
SERDES0_TX0_P | TX_P_LN0 | O | SerDes differential data transmit pins. Lane 0 | HiZ |
SERDES0_TX0_N | TX_M_LN0 | O | HiZ | |
SERDES0_RX1_P | RX_P_LN1 | I | SerDes differential data receive pins. Lane 1 | HiZ |
SERDES0_RX1_N | RX_M_LN1 | I | HiZ | |
SERDES0_TX1_P | TX_P_LN1 | O | SerDes differential data transmit pins. Lane 1 | HiZ |
SERDES0_TX1_N | TX_M_LN1 | O | HiZ | |
SERDES0_RX2_P | RX_P_LN2 | I | SerDes differential data receive pins. Lane 2 | HiZ |
SERDES0_RX2_N | RX_M_LN2 | I | HiZ | |
SERDES0_TX2_P | TX_P_LN2 | O | SerDes differential data transmit pins. Lane 2 | HiZ |
SERDES0_TX2_N | TX_M_LN2 | O | HiZ | |
SERDES0_RX3_P | RX_P_LN3 | I | SerDes differential data receive pins. Lane 3 | HiZ |
SERDES0_RX3_N | RX_M_LN3 | I | HiZ | |
SERDES0_TX3_P | TX_P_LN3 | O | SerDes differential data transmit pins. Lane 3 | HiZ |
SERDES0_TX3_N | TX_M_LN3 | O | HiZ | |
SERDES0_REFCLK_P | CMN_REFCLK_P | I/O | SerDes external system reference clock | HiZ |
SERDES0_REFCLK_N | CMN_REFCLK_N | I/O | HiZ | |
SERDES0_REXT | CMN_REXT | A/I | PMA external calibration resistor. Requires a 3.01 kOhm ±1% accurate off-chip resistor connected from this pin to ground. | HiZ |