SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-572 lists the memory-mapped registers for the UDMASS_INTA0_CFG. All register offset addresses not listed in Table 10-572 should be considered as reserved locations and the register contents should not be modified.
The Interrupt Aggregator Global Registers region is accessed by setting the cfg_rsel signal to 0 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG | 3080 2000h |
MCU_NAVSS0_UDMASS_INTA0_CFG | 283C 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_INTA0_CFG Physical Address | MCU_NAVSS0_UDMASS_INTA0_CFG Physical Address |
---|---|---|---|---|
0h | UDMA_INTA_REVISION | Revision Register | 3080 2000h | 283C 0000h |
8h | UDMA_INTA_INTCAP | Interrupt Capabilities | 3080 2008h | 283C 0008h |
10h | UDMA_INTA_AUXCAP | Auxiliary Capabilities | 3080 2010h | 283C 0010h |
UDMA_INTA_REVISION is shown in Figure 10-211 and described in Table 10-574.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG | 3080 2000h |
MCU_NAVSS0_UDMASS_INTA0_CFG | 283C 0000h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R-6696h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-Ah | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-32 | RESERVED | R | X | |
31-16 | MODID | R | 6696h | Module ID field |
15-11 | REVRTL | R | Ah | RTL revisioн |
10-8 | REVMAJ | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom revision |
5-0 | REVMIN | R | 0h | Minor revision |
UDMA_INTA_INTCAP is shown in Figure 10-212 and described in Table 10-576.
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The IntCap Register contains information on virtual interrupts.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG | 3080 2008h |
MCU_NAVSS0_UDMASS_INTA0_CFG | 283C 0008h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||||||||||||||||||||||||||
R-X | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VINTR_CNT | SEVT_CNT | ||||||||||||||||||||||||||||||
R-100h | R-1200h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-32 | RESERVED | R | X | |
31-16 | VINTR_CNT | R | 100h | Virtual interrupt register/pin count |
15-0 | SEVT_CNT | R | 1200h | Number of 'event to virt int' mapping registers. NOTE: This value is 600h for MCU_NAVSS0_UDMASS_INTR_AGGR0 |
UDMA_INTA_AUXCAP is shown in Figure 10-213 and described in Table 10-578.
Return to Summary Table.
The AuxCap Register contains information on additional capabilities.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG | 3080 2010h |
MCU_NAVSS0_UDMASS_INTA0_CFG | 283C 0010h |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | MEVI_CNT | ||||||||||||||||||||||||||||||
R-X | R-200h | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVI_CNT | GEVI_CNT | ||||||||||||||||||||||||||||||
R-54h | R-200h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-48 | RESERVED | R | X | |
47-32 | MEVI_CNT | R | 200h | Number of multicast event registers NOTE: This value is 100h for MCU_NAVSS0_UDMASS_INTR_AGGR0 |
31-16 | LEVI_CNT | R | 54h | Local input events for local to global translation
|
15-0 | GEVI_CNT | R | 200h | Number of event counting registers NOTE: This value is 80h for MCU_NAVSS0_UDMASS_INTR_AGGR0 |