SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-1281 lists the memory-mapped registers for the SEC_MMR0_DBG_CTRL. All register offset addresses not listed in Table 5-1281 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
SEC_MMR0_DBG_CTRL | 4594 4000h |
Offset | Acronym | Register Name | SEC_MMR0_DBG_CTRL Physical Address |
---|---|---|---|
0h | CTRLMMR_SEC_CLSTR0_CORE0_DBG_CFG | Cluster0 Core0 Debug Configuration Register | 4594 4000h |
40h | CTRLMMR_SEC_CLSTR0_CORE1_DBG_CFG | Cluster0 Core1 Debug Configuration Register | 4594 4040h |
CTRLMMR_SEC_CLSTR0_CORE0_DBG_CFG is shown in Figure 5-627 and described in Table 5-1283.
Return to Summary Table.
Configures debug operation for Cluster Core0.
Instance | Physical Address |
---|---|
SEC_MMR0_DBG_CTRL | 4594 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBGEN | NIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | DBGEN | R/W | Ah | Core0 Invasive debug enable. |
11-8 | NIDEN | R/W | Ah | Core0 Non-invasive debug enable. |
7-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR0_CORE1_DBG_CFG is shown in Figure 5-628 and described in Table 5-1285.
Return to Summary Table.
Configures debug operation for Cluster Core1.
Instance | Physical Address |
---|---|
SEC_MMR0_DBG_CTRL | 4594 4040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBGEN | NIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | DBGEN | R/W | Ah | Core1 Invasive debug enable. |
11-8 | NIDEN | R/W | Ah | Core1 Non-invasive debug enable. |
7-0 | RESERVED | R | 0h | Reserved |