SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-1586 lists the MCU_PLL0_CFG registers. All register offset addresses not listed in Table 5-1586 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_PLL0_CFG | 40D0 0000h |
Offset | Acronym | Register Name | MCU_PLL0_CFG Physical Address |
---|---|---|---|
0h | MCU_PLL0_PID | Peripheral Identification Register | 40D0 0000h |
8h | MCU_PLL0_CFG | PLL MMR Configuration | 40D0 0008h |
10h | MCU_PLL0_LOCKKEY0 | PLL0 Lock Key 0 Register | 40D0 0010h |
14h | MCU_PLL0_LOCKKEY1 | PLL0 Lock Key 1 RegisterAddr | 40D0 0014h |
20h | MCU_PLL0_CTRL | PLL0 Control | 40D0 0020h |
24h | MCU_PLL0_STAT | PLL0 Status | 40D0 0024h |
30h | MCU_PLL0_FREQ_CTRL0 | PLL0 Frequency Control 0 Register | 40D0 0030h |
34h | MCU_PLL0_FREQ_CTRL1 | PLL0 Frequency Control 1 Register | 40D0 0034h |
38h | MCU_PLL0_DIV_CTRL | PLL0 Output Clock Divider Register | 40D0 0038h |
40h | MCU_PLL0_SS_CTRL | PLL_SS_CTRL register for PLL0 | 40D0 0040h |
44h | MCU_PLL0_SS_SPREAD | PLL_SS_SPREAD register for PLL0 | 40D0 0044h |
80h | MCU_PLL0_HSDIV_CTRL0 | HSDIV_CTRL0 register for PLL0 | 40D0 0080h |
84h | MCU_PLL0_HSDIV_CTRL1 | HSDIV_CTRL1 register for PLL0 | 40D0 0084h |
1000h | MCU_PLL1_PID | Peripheral Identification Register | 40D0 1000h |
1008h | MCU_PLL1_CFG | PLL MMR Configuration | 40D0 1008h |
1010h | MCU_PLL1_LOCKKEY0 | PLL1 Lock Key 0 Register | 40D0 1010h |
1014h | MCU_PLL1_LOCKKEY1 | PLL1 Lock Key 1 RegisterAddr | 40D0 1014h |
1020h | MCU_PLL1_CTRL | PLL1 Control | 40D0 1020h |
1024h | MCU_PLL1_STAT | PLL1 Status | 40D0 1024h |
1030h | MCU_PLL1_FREQ_CTRL0 | PLL1 Frequency Control 1 Register | 40D0 1030h |
1034h | MCU_PLL1_FREQ_CTRL1 | PLL0 Frequency Control 1 Register | 40D0 1034h |
1038h | MCU_PLL1_DIV_CTRL | PLL1 Output Clock Divider Register | 40D0 1038h |
1040h | MCU_PLL1_SS_CTRL | PLL_SS_CTRL register for PLL1 | 40D0 1040h |
1044h | MCU_PLL1_SS_SPREAD | PLL_SS_SPREAD register for PLL1 | 40D0 1044h |
1080h | MCU_PLL1_HSDIV_CTRL0 | HSDIV_CTRL0 register for PLL1 | 40D0 1080h |
1084h | MCU_PLL1_HSDIV_CTRL1 | HSDIV_CTRL1 register for PLL1 | 40D0 1084h |
1088h | MCU_PLL1_HSDIV_CTRL2 | HSDIV_CTRL2 register for PLL1 | 40D0 1088h |
108Ch | MCU_PLL1_HSDIV_CTRL3 | HSDIV_CTRL3 register for PLL1 | 40D0 108Ch |
1090h | MCU_PLL1_HSDIV_CTRL4 | HSDIV_CTRL4 register for PLL1 | 40D0 1090h |
2000h | MCU_PLL2_PID | Peripheral Identification Register | 40D0 2000h |
2008h | MCU_PLL2_CFG | PLL MMR Configuration | 40D0 2008h |
2010h | MCU_PLL2_LOCKKEY0 | PLL2 Lock Key 0 Register | 40D0 2010h |
2014h | MCU_PLL2_LOCKKEY1 | PLL2 Lock Key 1 RegisterAddr | 40D0 2014h |
2020h | MCU_PLL2_CTRL | PLL2 Control | 40D0 2020h |
2024h | MCU_PLL2_STAT | PLL2 Status | 40D0 2024h |
2030h | MCU_PLL2_FREQ_CTRL0 | PLL2 Frequency Control 2 Register | 40D0 2030h |
2034h | MCU_PLL2_FREQ_CTRL1 | PLL0 Frequency Control 1 Register | 40D0 2034h |
2038h | MCU_PLL2_DIV_CTRL | PLL2 Output Clock Divider Register | 40D0 2038h |
2040h | MCU_PLL2_SS_CTRL | PLL_SS_CTRL register for PLL2 | 40D0 2040h |
2044h | MCU_PLL2_SS_SPREAD | PLL_SS_SPREAD register for PLL2 | 40D0 2044h |
2080h | MCU_PLL2_HSDIV_CTRL0 | HSDIV_CTRL0 register for PLL2 | 40D0 2080h |
2084h | MCU_PLL2_HSDIV_CTRL1 | HSDIV_CTRL1 register for PLL2 | 40D0 2084h |
2088h | MCU_PLL2_HSDIV_CTRL2 | HSDIV_CTRL2 register for PLL2 | 40D0 2088h |
208Ch | MCU_PLL2_HSDIV_CTRL3 | HSDIV_CTRL3 register for PLL2 | 40D0 208Ch |
2090h | MCU_PLL2_HSDIV_CTRL4 | HSDIV_CTRL4 register for PLL2 | 40D0 2090h |
MCU_PLL0_PID is shown in Figure 5-766 and described in Table 5-1588.
Return to the Summary Table.
Peripheral Identification Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE | |||||||||||||
R-1h | R-2h | R-180h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MISC | MAJOR | CUSTOM | MINOR | ||||||||||||
R-2h | R-0h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Peripheral Identification Register Scheme |
29-28 | BU | R | 2h | Business Unit - Processors |
27-16 | MODULE | R | 180h | Module functional identifier |
15-11 | MISC | R | 2h | Misc revision number |
10-8 | MAJOR | R | 0h | Major revision number |
7-6 | CUSTOM | R | 0h | custom revision number |
5-0 | MINOR | R | 1h | Minor revision number |
MCU_PLL0_CFG is shown in Figure 5-767 and described in Table 5-1590.
Return to the Summary Table.
PLL MMR Configuration
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
HSDIV_PRSNT | |||||||
R-3h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
HSDIV_PRSNT | |||||||
R-3h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SSM_TYPE | RESERVED | SSM_WVTBL | ||||
R-0h | R-1h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_TYPE | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | HSDIV_PRSNT | R | 3h | High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock |
15-13 | RESERVED | R | X | Reserved |
12-11 | SSM_TYPE | R | 1h | Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved |
10-9 | RESERVED | R | X | Reserved |
8 | SSM_WVTBL | R | 0h | Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present |
7-2 | RESERVED | R | X | Reserved |
1-0 | PLL_TYPE | R | 0h | Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL |
MCU_PLL0_LOCKKEY0 is shown in Figure 5-768 and described in Table 5-1592.
Return to the Summary Table.
PLL0 Lock Key 0 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
KEY | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | UNLOCKED | ||||||
R/W-0h | R-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | KEY | R/W | 0h | Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers |
0 | UNLOCKED | R | 0h | Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing. |
MCU_PLL0_LOCKKEY1 is shown in Figure 5-769 and described in Table 5-1594.
Return to the Summary Table.
PLL0 Lock Key 1 RegisterAddr
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCKKEY1_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LOCKKEY1_VAL | R/W | 0h | Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers |
MCU_PLL0_CTRL is shown in Figure 5-770 and described in Table 5-1596.
Return to the Summary Table.
PLL0 Control
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYPASS_EN | RESERVED | ||||||
R/W-1h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BYP_ON_LOCKLOSS | ||||||
R-0h | R/W-1h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PLL_EN | RESERVED | INTL_BYP_EN | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_4PH_EN | CLK_POSTDIV_EN | RESERVED | DSM_EN | DAC_EN | ||
R-0h | R/W-0h | R/W-1h | R-0h | R/W-0h | R/W-1h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BYPASS_EN | R/W | 1h | Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs |
30-17 | RESERVED | R | X | Reserved |
16 | BYP_ON_LOCKLOSS | R/W | 1h | Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock |
15 | PLL_EN | R/W | 0h | PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled |
14-9 | RESERVED | R | X | Reserved |
8 | INTL_BYP_EN | R/W | 0h | PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock |
7-6 | RESERVED | R | X | Reserved |
5 | CLK_4PH_EN | R/W | 0h | Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled. |
4 | CLK_POSTDIV_EN | R/W | 1h | Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled. |
3-2 | RESERVED | R | X | Reserved |
1 | DSM_EN | R/W | 0h | Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode) |
0 | DAC_EN | R/W | 1h | Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode) |
MCU_PLL0_STAT is shown in Figure 5-771 and described in Table 5-1598.
Return to the Summary Table.
PLL0 Status
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | Reserved |
0 | LOCK | R | 0h | PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked |
MCU_PLL0_FREQ_CTRL0 is shown in Figure 5-772 and described in Table 5-1600.
Return to the Summary Table.
PLL0 Frequency Control 0 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FB_DIV_INT | ||||||||||||||||||||||||||||||
R-0h | R/W-10h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11-0 | FB_DIV_INT | R/W | 10h | PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported |
MCU_PLL0_FREQ_CTRL1 is shown in Figure 5-773 and described in Table 5-1602.
Return to the Summary Table.
PLL0 Frequency Control 1 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FB_DIV_FRAC | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | X | Reserved |
23-0 | FB_DIV_FRAC | R/W | 0h | PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (224)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(224)) 24'h000002 - .000000119209 (2/(224)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(224)) |
MCU_PLL0_DIV_CTRL is shown in Figure 5-774 and described in Table 5-1604.
Return to the Summary Table.
PLL0 Output Clock Divider Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | POST_DIV2 | RESERVED | POST_DIV1 | ||||||||||||
R-0h | R/W-1h | R-0h | R/W-2h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REF_DIV | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | X | Reserved |
26-24 | POST_DIV2 | R/W | 1h | Secondary post divider. Supports values of 1-7 |
23-19 | RESERVED | R | X | Reserved |
18-16 | POST_DIV1 | R/W | 2h | Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7 |
15-6 | RESERVED | R | X | Reserved |
5-0 | REF_DIV | R/W | 1h | Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63 |
MCU_PLL0_SS_CTRL is shown in Figure 5-775 and described in Table 5-1606.
Return to the Summary Table.
PLL_SS_CTRL register for PLL0
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYPASS_EN | RESERVED | WV_TBLE_MAXADDR | |||||
R/W-1h | R-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WV_TBLE_MAXADDR | RESERVED | ||||||
R/W-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DOWNSPREAD_EN | RESERVED | WAVE_SEL | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BYPASS_EN | R/W | 1h | Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency |
30-26 | RESERVED | R | X | Reserved |
25-18 | WV_TBLE_MAXADDR | R/W | 0h | Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0 |
17-16 | RESERVED | R | X | Reserved |
15 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in reset |
14-5 | RESERVED | R | X | Reserved |
4 | DOWNSPREAD_EN | R/W | 0h | Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread |
3-1 | RESERVED | R | X | Reserved |
0 | WAVE_SEL | R/W | 0h | Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table |
MCU_PLL0_SS_SPREAD is shown in Figure 5-776 and described in Table 5-1608.
Return to the Summary Table.
PLL_SS_SPREAD register for PLL0
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MOD_DIV | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPREAD | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | Reserved |
19-16 | MOD_DIV | R/W | 1h | Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63 |
15-5 | RESERVED | R | X | Reserved |
4-0 | SPREAD | R/W | 1h | Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1% |
MCU_PLL0_HSDIV_CTRL0 is shown in Figure 5-777 and described in Table 5-1610.
Return to the Summary Table.
HSDIV_CTRL0 register for PLL0
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL0_HSDIV_CTRL1 is shown in Figure 5-778 and described in Table 5-1612.
Return to the Summary Table.
HSDIV_CTRL1 register for PLL0
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL1_PID is shown in Figure 5-779 and described in Table 5-1614.
Return to the Summary Table.
Peripheral Identification Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE | |||||||||||||
R-1h | R-2h | R-180h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MISC | MAJOR | CUSTOM | MINOR | ||||||||||||
R-2h | R-0h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Peripheral Identification Register Scheme |
29-28 | BU | R | 2h | Business Unit - Processors |
27-16 | MODULE | R | 180h | Module functional identifier |
15-11 | MISC | R | 2h | Misc revision number |
10-8 | MAJOR | R | 0h | Major revision number |
7-6 | CUSTOM | R | 0h | custom revision number |
5-0 | MINOR | R | 1h | Minor revision number |
MCU_PLL1_CFG is shown in Figure 5-780 and described in Table 5-1616.
Return to the Summary Table.
PLL MMR Configuration
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
HSDIV_PRSNT | |||||||
R-1Fh | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
HSDIV_PRSNT | |||||||
R-1Fh | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SSM_TYPE | RESERVED | SSM_WVTBL | ||||
R-0h | R-1h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_TYPE | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | HSDIV_PRSNT | R | 1Fh | High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock |
15-13 | RESERVED | R | X | Reserved |
12-11 | SSM_TYPE | R | 1h | Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved |
10-9 | RESERVED | R | X | Reserved |
8 | SSM_WVTBL | R | 0h | Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present |
7-2 | RESERVED | R | X | Reserved |
1-0 | PLL_TYPE | R | 0h | Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL |
MCU_PLL1_LOCKKEY0 is shown in Figure 5-781 and described in Table 5-1618.
Return to the Summary Table.
PLL1 Lock Key 0 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
KEY | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | UNLOCKED | ||||||
R/W-0h | R-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | KEY | R/W | 0h | Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers |
0 | UNLOCKED | R | 0h | Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing. |
MCU_PLL1_LOCKKEY1 is shown in Figure 5-782 and described in Table 5-1620.
Return to the Summary Table.
PLL1 Lock Key 1 RegisterAddr
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCKKEY1_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LOCKKEY1_VAL | R/W | 0h | Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers |
MCU_PLL1_CTRL is shown in Figure 5-783 and described in Table 5-1622.
Return to the Summary Table.
PLL1 Control
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYPASS_EN | RESERVED | ||||||
R/W-1h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BYP_ON_LOCKLOSS | ||||||
R-0h | R/W-1h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PLL_EN | RESERVED | INTL_BYP_EN | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_4PH_EN | CLK_POSTDIV_EN | RESERVED | DSM_EN | DAC_EN | ||
R-0h | R/W-0h | R/W-1h | R-0h | R/W-0h | R/W-1h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BYPASS_EN | R/W | 1h | Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs |
30-17 | RESERVED | R | X | Reserved |
16 | BYP_ON_LOCKLOSS | R/W | 1h | Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock |
15 | PLL_EN | R/W | 0h | PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled |
14-9 | RESERVED | R | X | Reserved |
8 | INTL_BYP_EN | R/W | 0h | PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock |
7-6 | RESERVED | R | X | Reserved |
5 | CLK_4PH_EN | R/W | 0h | Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled. |
4 | CLK_POSTDIV_EN | R/W | 1h | Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled. |
3-2 | RESERVED | R | X | Reserved |
1 | DSM_EN | R/W | 0h | Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode) |
0 | DAC_EN | R/W | 1h | Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode) |
MCU_PLL1_STAT is shown in Figure 5-784 and described in Table 5-1624.
Return to the Summary Table.
PLL1 Status
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | Reserved |
0 | LOCK | R | 0h | PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked |
MCU_PLL1_FREQ_CTRL0 is shown in Figure 5-785 and described in Table 5-1626.
Return to the Summary Table.
PLL1 Frequency Control 1 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FB_DIV_INT | ||||||||||||||||||||||||||||||
R-0h | R/W-10h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11-0 | FB_DIV_INT | R/W | 10h | PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported |
MCU_PLL1_FREQ_CTRL1 is shown in Figure 5-786 and described in Table 5-1628.
Return to the Summary Table.
PLL0 Frequency Control 1 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FB_DIV_FRAC | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | X | Reserved |
23-0 | FB_DIV_FRAC | R/W | 0h | PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (224)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(224)) 24'h000002 - .000000119209 (2/(224)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(224)) |
MCU_PLL1_DIV_CTRL is shown in Figure 5-787 and described in Table 5-1630.
Return to the Summary Table.
PLL1 Output Clock Divider Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | POST_DIV2 | RESERVED | POST_DIV1 | ||||||||||||
R-0h | R/W-1h | R-0h | R/W-2h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REF_DIV | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | X | Reserved |
26-24 | POST_DIV2 | R/W | 1h | Secondary post divider. Supports values of 1-7 |
23-19 | RESERVED | R | X | Reserved |
18-16 | POST_DIV1 | R/W | 2h | Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7 |
15-6 | RESERVED | R | X | Reserved |
5-0 | REF_DIV | R/W | 1h | Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63 |
MCU_PLL1_SS_CTRL is shown in Figure 5-788 and described in Table 5-1632.
Return to the Summary Table.
PLL_SS_CTRL register for PLL1
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYPASS_EN | RESERVED | WV_TBLE_MAXADDR | |||||
R/W-1h | R-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WV_TBLE_MAXADDR | RESERVED | ||||||
R/W-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DOWNSPREAD_EN | RESERVED | WAVE_SEL | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BYPASS_EN | R/W | 1h | Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency |
30-26 | RESERVED | R | X | Reserved |
25-18 | WV_TBLE_MAXADDR | R/W | 0h | Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0 |
17-16 | RESERVED | R | X | Reserved |
15 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in reset |
14-5 | RESERVED | R | X | Reserved |
4 | DOWNSPREAD_EN | R/W | 0h | Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread |
3-1 | RESERVED | R | X | Reserved |
0 | WAVE_SEL | R/W | 0h | Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table |
MCU_PLL1_SS_SPREAD is shown in Figure 5-789 and described in Table 5-1634.
Return to the Summary Table.
PLL_SS_SPREAD register for PLL1
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MOD_DIV | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPREAD | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | Reserved |
19-16 | MOD_DIV | R/W | 1h | Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63 |
15-5 | RESERVED | R | X | Reserved |
4-0 | SPREAD | R/W | 1h | Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1% |
MCU_PLL1_HSDIV_CTRL0 is shown in Figure 5-790 and described in Table 5-1636.
Return to the Summary Table.
HSDIV_CTRL0 register for PLL1
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL1_HSDIV_CTRL1 is shown in Figure 5-791 and described in Table 5-1638.
Return to the Summary Table.
HSDIV_CTRL1 register for PLL1
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL1_HSDIV_CTRL2 is shown in Figure 5-792 and described in Table 5-1640.
Return to the Summary Table.
HSDIV_CTRL2 register for PLL1
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL1_HSDIV_CTRL3 is shown in Figure 5-793 and described in Table 5-1642.
Return to the Summary Table.
HSDIV_CTRL3 register for PLL1
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 108Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL1_HSDIV_CTRL4 is shown in Figure 5-794 and described in Table 5-1644.
Return to the Summary Table.
HSDIV_CTRL4 register for PLL1
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 1090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL2_PID is shown in Figure 5-795 and described in Table 5-1646.
Return to the Summary Table.
Peripheral Identification Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE | |||||||||||||
R-1h | R-2h | R-180h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MISC | MAJOR | CUSTOM | MINOR | ||||||||||||
R-2h | R-0h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Peripheral Identification Register Scheme |
29-28 | BU | R | 2h | Business Unit - Processors |
27-16 | MODULE | R | 180h | Module functional identifier |
15-11 | MISC | R | 2h | Misc revision number |
10-8 | MAJOR | R | 0h | Major revision number |
7-6 | CUSTOM | R | 0h | custom revision number |
5-0 | MINOR | R | 1h | Minor revision number |
MCU_PLL2_CFG is shown in Figure 5-796 and described in Table 5-1648.
Return to the Summary Table.
PLL MMR Configuration
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
HSDIV_PRSNT | |||||||
R-1Fh | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
HSDIV_PRSNT | |||||||
R-1Fh | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SSM_TYPE | RESERVED | SSM_WVTBL | ||||
R-0h | R-1h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_TYPE | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | HSDIV_PRSNT | R | 1Fh | High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock |
15-13 | RESERVED | R | X | Reserved |
12-11 | SSM_TYPE | R | 1h | Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved |
10-9 | RESERVED | R | X | Reserved |
8 | SSM_WVTBL | R | 0h | Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present |
7-2 | RESERVED | R | X | Reserved |
1-0 | PLL_TYPE | R | 0h | Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL |
MCU_PLL2_LOCKKEY0 is shown in Figure 5-797 and described in Table 5-1650.
Return to the Summary Table.
PLL2 Lock Key 0 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
KEY | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | UNLOCKED | ||||||
R/W-0h | R-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | KEY | R/W | 0h | Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers |
0 | UNLOCKED | R | 0h | Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing. |
MCU_PLL2_LOCKKEY1 is shown in Figure 5-798 and described in Table 5-1652.
Return to the Summary Table.
PLL2 Lock Key 1 RegisterAddr
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCKKEY1_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LOCKKEY1_VAL | R/W | 0h | Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers |
MCU_PLL2_CTRL is shown in Figure 5-799 and described in Table 5-1654.
Return to the Summary Table.
PLL2 Control
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYPASS_EN | RESERVED | ||||||
R/W-1h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BYP_ON_LOCKLOSS | ||||||
R-0h | R/W-1h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PLL_EN | RESERVED | INTL_BYP_EN | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_4PH_EN | CLK_POSTDIV_EN | RESERVED | DSM_EN | DAC_EN | ||
R-0h | R/W-0h | R/W-1h | R-0h | R/W-0h | R/W-1h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BYPASS_EN | R/W | 1h | Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs |
30-17 | RESERVED | R | X | Reserved |
16 | BYP_ON_LOCKLOSS | R/W | 1h | Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock |
15 | PLL_EN | R/W | 0h | PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled |
14-9 | RESERVED | R | X | Reserved |
8 | INTL_BYP_EN | R/W | 0h | PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock |
7-6 | RESERVED | R | X | Reserved |
5 | CLK_4PH_EN | R/W | 0h | Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled. |
4 | CLK_POSTDIV_EN | R/W | 1h | Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled. |
3-2 | RESERVED | R | X | Reserved |
1 | DSM_EN | R/W | 0h | Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode) |
0 | DAC_EN | R/W | 1h | Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode) |
MCU_PLL2_STAT is shown in Figure 5-800 and described in Table 5-1656.
Return to the Summary Table.
PLL2 Status
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | Reserved |
0 | LOCK | R | 0h | PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked |
MCU_PLL2_FREQ_CTRL0 is shown in Figure 5-801 and described in Table 5-1658.
Return to the Summary Table.
PLL2 Frequency Control 2 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FB_DIV_INT | ||||||||||||||||||||||||||||||
R-0h | R/W-10h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11-0 | FB_DIV_INT | R/W | 10h | PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported |
MCU_PLL2_FREQ_CTRL1 is shown in Figure 5-802 and described in Table 5-1660.
Return to the Summary Table.
PLL0 Frequency Control 1 Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FB_DIV_FRAC | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | X | Reserved |
23-0 | FB_DIV_FRAC | R/W | 0h | PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (224)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(224)) 24'h000002 - .000000119209 (2/(224)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(224)) |
MCU_PLL2_DIV_CTRL is shown in Figure 5-803 and described in Table 5-1662.
Return to the Summary Table.
PLL2 Output Clock Divider Register
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | POST_DIV2 | RESERVED | POST_DIV1 | ||||||||||||
R-0h | R/W-1h | R-0h | R/W-2h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REF_DIV | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | X | Reserved |
26-24 | POST_DIV2 | R/W | 1h | Secondary post divider. Supports values of 1-7 |
23-19 | RESERVED | R | X | Reserved |
18-16 | POST_DIV1 | R/W | 2h | Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7 |
15-6 | RESERVED | R | X | Reserved |
5-0 | REF_DIV | R/W | 1h | Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63 |
MCU_PLL2_SS_CTRL is shown in Figure 5-804 and described in Table 5-1664.
Return to the Summary Table.
PLL_SS_CTRL register for PLL2
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYPASS_EN | RESERVED | WV_TBLE_MAXADDR | |||||
R/W-1h | R-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WV_TBLE_MAXADDR | RESERVED | ||||||
R/W-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DOWNSPREAD_EN | RESERVED | WAVE_SEL | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BYPASS_EN | R/W | 1h | Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency |
30-26 | RESERVED | R | X | Reserved |
25-18 | WV_TBLE_MAXADDR | R/W | 0h | Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0 |
17-16 | RESERVED | R | X | Reserved |
15 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in reset |
14-5 | RESERVED | R | X | Reserved |
4 | DOWNSPREAD_EN | R/W | 0h | Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread |
3-1 | RESERVED | R | X | Reserved |
0 | WAVE_SEL | R/W | 0h | Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table |
MCU_PLL2_SS_SPREAD is shown in Figure 5-805 and described in Table 5-1666.
Return to the Summary Table.
PLL_SS_SPREAD register for PLL2
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MOD_DIV | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPREAD | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | Reserved |
19-16 | MOD_DIV | R/W | 1h | Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63 |
15-5 | RESERVED | R | X | Reserved |
4-0 | SPREAD | R/W | 1h | Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1% |
MCU_PLL2_HSDIV_CTRL0 is shown in Figure 5-806 and described in Table 5-1668.
Return to the Summary Table.
HSDIV_CTRL0 register for PLL2
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL2_HSDIV_CTRL1 is shown in Figure 5-807 and described in Table 5-1670.
Return to the Summary Table.
HSDIV_CTRL1 register for PLL2
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL2_HSDIV_CTRL2 is shown in Figure 5-808 and described in Table 5-1672.
Return to the Summary Table.
HSDIV_CTRL2 register for PLL2
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL2_HSDIV_CTRL3 is shown in Figure 5-809 and described in Table 5-1674.
Return to the Summary Table.
HSDIV_CTRL3 register for PLL2
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 208Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |
MCU_PLL2_HSDIV_CTRL4 is shown in Figure 5-810 and described in Table 5-1676.
Return to the Summary Table.
HSDIV_CTRL4 register for PLL2
Instance | Physical Address |
---|---|
MCU_PLL0_CFG | 40D0 2090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESET | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKOUT_EN | RESERVED | SYNC_DIS | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSDIV | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl |
30-16 | RESERVED | R | X | Reserved |
15 | CLKOUT_EN | R/W | 0h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 |
14-9 | RESERVED | R | X | Reserved |
8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous |
7 | RESERVED | R | X | Reserved |
6-0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 |