SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-460 lists the memory-mapped registers for the NAVSS0_UDMASS_RINGACC0_SRC_FIFOS. All register offset addresses not listed in Table 10-460 should be considered as reserved locations and the register contents should not be modified.
The Ring Accelerator Queues Registers region is accessed by setting the cfg_crsel signal to 0 during the access. This region provides a set of contigous 512-byte windows for accessing the rings in a FIFO like manner. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS | 3800 0000h |
MCU_NAVSS0_UDMASS_RINGACC0_FIFOS | 2B00 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Physical Address | MCU_NAVSS0_UDMASS_RINGACC0_FIFOS Physical Address |
---|---|---|---|---|
0h + formula | RINGACC_RINGHEADDATA_j_y | Ring Head Entry Data Registers | 3800 0000h + formula | 2B00 0000h + formula |
200h + formula | RINGACC_RINGTAILDATA_j_y | Ring Tail Entry Data Registers | 3800 0200h + formula | 2B00 0200h + formula |
400h + formula | RINGACC_PEEKHEADDATA_j_y | Ring Peek Head Entry Data Registers | 3800 0400h + formula | 2B00 0400h + formula |
600h + formula | RINGACC_PEEKTAILDATA_j_y | Ring Peek Tail Entry Data Registers | 3800 0600h + formula | 2B00 0600h + formula |
RINGACC_RINGHEADDATA_j_y is shown in Figure 10-171 and described in Table 10-462.
Return to Summary Table.
The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring head element for reads or writes. The data is right justified.)
Offset = 0h + (j * 1000h) + (y * 4h); where
j = 0h to 331h, y = 0h to 7Fh for NAVSS0_UDMASS_RINGACC0_SRC_FIFOS
j = 0h to 11Dh, y = 0h to 7Fh for MCU_NAVSS0_UDMASS_RINGACC0_FIFOS
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS | 3800 0000h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_FIFOS | 2B00 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Block of ring head element data |
RINGACC_RINGTAILDATA_j_y is shown in Figure 10-172 and described in Table 10-464.
Return to Summary Table.
The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring tail element for reads or writes. The data is right justified.)
Offset = 200h + (j * 1000h) + (y * 4h); where
j = 0h to 331h, y = 0h to 7Fh for NAVSS0_UDMASS_RINGACC0_SRC_FIFOS
j = 0h to 11Dh, y = 0h to 7Fh for MCU_NAVSS0_UDMASS_RINGACC0_FIFOS
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS | 3800 0200h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_FIFOS | 2B00 0200h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Block of ring tail element data |
RINGACC_PEEKHEADDATA_j_y is shown in Figure 10-173 and described in Table 10-466.
Return to Summary Table.
The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring head element for reads. Writes are ignored. The data is right justified.)
Offset = 400h + (j * 1000h) + (y * 4h); where
j = 0h to 331h, y = 0h to 7Fh for NAVSS0_UDMASS_RINGACC0_SRC_FIFOS
j = 0h to 11Dh, y = 0h to 7Fh for MCU_NAVSS0_UDMASS_RINGACC0_FIFOS
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS | 3800 0400h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_FIFOS | 2B00 0400h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Block of ring head element data. Not supported in ring mode. |
RINGACC_PEEKTAILDATA_j_y is shown in Figure 10-174 and described in Table 10-468.
Return to Summary Table.
The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring tail element for reads. Writes are ignored. The data is right justified.)
Offset = 600h + (j * 1000h) + (y * 4h); where
j = 0h to 331h, y = 0h to 7Fh for NAVSS0_UDMASS_RINGACC0_SRC_FIFOS
j = 0h to 11Dh, y = 0h to 7Fh for MCU_NAVSS0_UDMASS_RINGACC0_FIFOS
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS | 3800 0600h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_FIFOS | 2B00 0600h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Block of ring tail element data. Not supported in ring mode. |