SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-741 describes power-management features available for the UART.
For information about source clock gating and the sleep/wake-up transitions description, see Power, in the Device Configuration.
Feature | Registers | Description |
---|---|---|
Clock autogating | ||
Peripheral idle modes | ||
Clock activity | N/A | Feature not available |
Controller standby modes | N/A | Feature not available |
Global wake-up enable | UART_SYSC[2] ENAWAKEUP | This bit enables the wake-up feature at module level. |
Wake-Up sources enable | N/A | Feature not available |