SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 6-175 lists the memory-mapped registers for the R5FSS_CCMR5. All register offset addresses not listed in Table 6-175 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_R5FSS0_COMPARE_CFG | 400F 0000h |
R5FSS0_COMPARE_CFG | 05B0 0000h |
Offset | Acronym | Register Name | MCU_R5FSS0_ COMPARE_CFG Physical Address |
---|---|---|---|
0h | R5FSS_CCMSR1 | CPU output compare status register | 400F 0000h |
4h | R5FSS_CCMKEYR1 | CPU output compare key register | 400F 0004h |
10h | R5FSS_CCMSR3 | Inactivity monitor status register | 400F 0010h |
14h | R5FSS_CCMKEYR3 | Inactivity monitor key register | 400F 0014h |
18h | R5FSS_CCMPOLCNTRL | Polarity control register | 400F 0018h |
Offset | Acronym | Register Name | R5FSS0_ COMPARE_CFG Physical Address |
---|---|---|---|
0h | R5FSS_CCMSR1 | CPU output compare status register | 05B0 0000h |
4h | R5FSS_CCMKEYR1 | CPU output compare key register | 05B0 0004h |
10h | R5FSS_CCMSR3 | Inactivity monitor status register | 05B0 0010h |
14h | R5FSS_CCMKEYR3 | Inactivity monitor key register | 05B0 0014h |
18h | R5FSS_CCMPOLCNTRL | Polarity control register | 05B0 0018h |
R5FSS_CCMSR1 is shown in Figure 6-73 and described in Table 6-178.
Return to Summary Table.
This register shows the error and self-test status of the CPU output compare block.
Instance | Physical Address |
---|---|
MCU_R5FSS0_COMPARE_CFG | 400F 0000h |
R5FSS0_COMPARE_CFG | 05B0 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CMPE1 | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STC1 | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STET1 | STE1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
16 | CMPE1 | R/W | 0h | Compare error for CPU output compare diagnostic. |
15-9 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
8 | STC1 | R/W | 0h | Self-test complete for CPU output compare diagnostic. |
7-2 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
1 | STET1 | R/W | 0h | Self-test error type for CPU output compare diagnostic. |
0 | STE1 | R/W | 0h | Self-test error for CPU output compare diagnostic. |
R5FSS_CCMKEYR1 is shown in Figure 6-74 and described in Table 6-180.
Return to Summary Table.
This register is used to select the operating mode of the CPU output compare block.
Instance | Physical Address |
---|---|
MCU_R5FSS0_COMPARE_CFG | 400F 0004h |
R5FSS0_COMPARE_CFG | 05B0 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MKEY1 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
3-0 | MKEY1 | R/W | 0h | Mode key to select operation for CPU output compare diagnostic. |
R5FSS_CCMSR3 is shown in Figure 6-75 and described in Table 6-182.
Return to Summary Table.
This register shows the error and self-test status of the inactivity monitor block.
Instance | Physical Address |
---|---|
MCU_R5FSS0_COMPARE_CFG | 400F 0010h |
R5FSS0_COMPARE_CFG | 05B0 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CMPE3 | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STC3 | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STET3 | STE3 | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
16 | CMPE3 | R/W | 0h | Compare error for inactivity monitor. |
15-9 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
8 | STC3 | R/W | 0h | Self-test complete for inactivity monitor. |
7-2 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
1 | STET3 | R/W | 0h | Self-test error type for inactivity monitor. |
0 | STE3 | R/W | 0h | Self-test error for inactivity monitor. |
R5FSS_CCMKEYR3 is shown in Figure 6-76 and described in Table 6-184.
Return to Summary Table.
This register is used to select the operating mode of the inactivity monitor block.
Instance | Physical Address |
---|---|
MCU_R5FSS0_COMPARE_CFG | 400F 0014h |
R5FSS0_COMPARE_CFG | 05B0 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MKEY3 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
3-0 | MKEY3 | R/W | 0h | Mode key to select operation for CPU output compare diagnostic. |
R5FSS_CCMPOLCNTRL is shown in Figure 6-77 and described in Table 6-186.
Return to Summary Table.
This register is used for polarity inversion of CPU compare signals.
Instance | Physical Address |
---|---|
MCU_R5FSS0_COMPARE_CFG | 400F 0018h |
R5FSS0_COMPARE_CFG | 05B0 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POL_INV | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
7-0 | POL_INV | R/W | 0h | Polarity inversion. This value is used to invert one of the 8 output compare signals from CPU1 to the R5FSS_CCMR5. Inverting any one signal will lead to compare error by the CPU output compare diagnostic. |