SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-673 lists the memory-mapped registers for the NAVSS0_NBSS_NB_CFG_MMRS. All register offset addresses not listed in Table 10-673 should be considered as reserved locations and the register contents should not be modified.
Config port registers
Instance | Base Address |
---|---|
NAVSS0_NBSS_NB0_CFG_MMRS | 0380 2000h |
NAVSS0_NBSS_NB1_CFG_MMRS | 0380 3000h |
Offset | Acronym | Register Name | NAVSS0_NBSS_NB0_CFG_MMRS Physical Address | NAVSS0_NBSS_NB1_CFG_MMRS Physical Address |
---|---|---|---|---|
0h | NB_PID | Revision Register | 0380 2000h | 0380 3000h |
10h | NB_THREADMAP | Thread Map Register | 0380 2010h | 0380 3010h |
NB_PID is shown in Figure 10-250 and described in Table 10-675.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
NAVSS0_NBSS_NB0_CFG_MMRS | 0380 2000h |
NAVSS0_NBSS_NB1_CFG_MMRS | 0380 3000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R-1h | R-2h | R-610h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-1Ah | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | PID register scheme |
29-28 | BU | R | 2h | BU |
27-16 | FUNC | R | 610h | Module ID |
15-11 | RTL | R | 1Ah | RTL revision. Will vary depending on release. |
10-8 | MAJOR | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 0h | Minor revision |
NB_THREADMAP is shown in Figure 10-251 and described in Table 10-677.
Return to Summary Table.
The Thread Map Register defines the VBUSM.C thread for each VBUSM source.
Instance | Physical Address |
---|---|
NAVSS0_NBSS_NB0_CFG_MMRS | 0380 2010h |
NAVSS0_NBSS_NB1_CFG_MMRS | 0380 3010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THREADMAP | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | THREADMAP | R/W | 0h | Thread map, each bit is for each VBUSM source. Bit [0] maps orderid 0-7 to VBUSM.C thread number. Bit [1] maps orderid 8-15 to VBUSM.C thread number. 0: VBUSM.C thread 0 (non-real time traffic) 1: VBUSM.C thread 2 (real-time traffic) |