SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are two SRAMs (each with size 4 KB - 512 words × 64-bit) in each MMCSD Subsystem. One SRAM dedicated for transmit and one SRAM dedicated for receive operations.
Figure 12-2208 shows the ECC Aggregator block diagram.
For more information about ECC Aggregator Registers, refer to MMCSD Registers.