Each I3C module has the following features:
- Communication Modes:
- Single Data Rate (SDR) mode
- High Data Rate – Dual Data Rate (HD-DDR) mode
- Bus Modes:
- Pure Bus Mode (supports only I3C devices). Maximum supported frequency is 10.375 MHz
- Master and Multi-Master modes
- Secondary master and slave modes
- Common Command Codes (CCC)
- Bus Enumeration and Discovery:
- Slaves implement standardized characteristics registers that can be queried by the master after power up to enumerate the devices attached to the bus.
- Hot-Join capability:
- A slave device can be powered on and join the bus after initial enumeration.
- In Band Interrupts (IBI):
- Slave devices request interrupts through the I3C bus rather than with separate side-band signals. This reduces the total IO count of the SoC as well as PCB routing.
- Dynamic Address Assignment (DAA):
- The master can assign each slave device an address during configuration. This supports IBI because interrupt priority among slaves is arbitrated with the same address arbitration scheme that is used for all communication.
- Static Addressing (SA)
- FIFO Buffers:
- CMD Queueing out going commands:
- CMD0_FIFO stores the least significant half-word of the command
- CMD1_FIFO stores the most significant half-word of the command
- TXFIFO stores data transmitted with each command
- RXFIFO stores data received as command response
- IBI_DATA_FIFO stores data received as part of the in-band-interrupt transfer (IBI can transfer 0, 1, or N bytes of data payload depending on the slave)
- Immediate high priority command queue
- Registers to store the parameters for the response to an IBI interrupt from a number of slaves:
- Each register holds the slave address and appropriate response type and payload length information for two different slaves, so that the controller can process in band interrupts without CPU intervention.