SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
As shown in Figure 5-760 and Figure 5-761 for each type of PLL, the reference clock (FREF) input is used to generate the synthesized clock, but can also be used as the bypass clock for some outputs of the PLL whenever the PLL enters bypass mode. It is mandatory for the PLL clock synthesis.