SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5082 lists the memory-mapped registers for the EPWM modules. All register offset addresses not listed in Table 12-5082 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
EHRPWM0_EPWM | 0300 0000h |
EHRPWM1_EPWM | 0301 0000h |
EHRPWM2_EPWM | 0302 0000h |
EHRPWM3_EPWM | 0303 0000h |
EHRPWM4_EPWM | 0304 0000h |
EHRPWM5_EPWM | 0305 0000h |
EHRPWM0_EHRPWM | 0300 8000h |
EHRPWM1_EHRPWM | 0301 8000h |
EHRPWM2_EHRPWM | 0302 8000h |
EHRPWM3_EHRPWM | 0303 8000h |
EHRPWM4_EHRPWM | 0304 8000h |
EHRPWM5_EHRPWM | 0305 8000h |
Offset | Acronym | Register Name | EHRPWM0_EPWM Physical Address | EHRPWM1_EPWM Physical Address | EHRPWM2_EPWM Physical Address |
---|---|---|---|---|---|
0h | EPWM_TBCTL | Time-Base Control Register | 0300 0000h | 0301 0000h | 0302 0000h |
2h | EPWM_TBSTS | Time-Base Status Register | 0300 0002h | 0301 0002h | 0302 0002h |
4h | HRPWM_TBPHSHR | Time-Base Phase High-Resolution PWM Register | 0300 0004h | 0301 0004h | 0302 0004h |
6h | EPWM_TBPHS | Time-Base Counter Phase Register | 0300 0006h | 0301 0006h | 0302 0006h |
8h | EPWM_TBCNT | Time-Base Counter Register | 0300 0008h | 0301 0008h | 0302 0008h |
Ah | EPWM_TBPRD | Time-Base Period Register | 0300 000Ah | 0301 000Ah | 0302 000Ah |
Eh | EPWM_CMPCTL | Counter-Compare Control Register | 0300 000Eh | 0301 000Eh | 0302 000Eh |
10h | HRPWM_CMPAHR | Counter-Compare A High-Resolution Register | 0300 0010h | 0301 0010h | 0302 0010h |
12h | EPWM_CMPA | Counter-Compare A Register | 0300 0012h | 0301 0012h | 0302 0012h |
14h | EPWM_CMPB | Counter-Compare B Register | 0300 0014h | 0301 0014h | 0302 0014h |
16h | EPWM_AQCTLA | Action Qualifier Control Register for Output A | 0300 0016h | 0301 0016h | 0302 0016h |
18h | EPWM_AQCTLB | Action Qualifier Control Register for Output B | 0300 0018h | 0301 0018h | 0302 0018h |
1Ah | EPWM_AQSFRC | Action Qualifier Software Force Register | 0300 001Ah | 0301 001Ah | 0302 001Ah |
1Ch | EPWM_AQCSFRC | Action Qualifier Continuous Software Force Register | 0300 001Ch | 0301 001Ch | 0302 001Ch |
1Eh | EPWM_DBCTL | Dead Band Generator Control Register | 0300 001Eh | 0301 001Eh | 0302 001Eh |
20h | EPWM_DBRED | Dead Band Generator Rising Edge Delay Count Register | 0300 0020h | 0301 0020h | 0302 0020h |
22h | EPWM_DBFED | Dead Band Generator Falling Edge Delay Count Register | 0300 0022h | 0301 0022h | 0302 0022h |
24h | EPWM_TZSEL | Trip-zone Select Register | 0300 0024h | 0301 0024h | 0302 0024h |
28h | EPWM_TZCTL | Trip-zone Control Register | 0300 0028h | 0301 0028h | 0302 0028h |
2Ah | EPWM_TZEINT | Trip-zone Enable Interrupt Register | 0300 002Ah | 0301 002Ah | 0302 002Ah |
2Ch | EPWM_TZFLG | Trip-zone Flag Register | 0300 002Ch | 0301 002Ch | 0302 002Ch |
2Eh | EPWM_TZCLR | Trip-zone Clear Register | 0300 002Eh | 0301 002Eh | 0302 002Eh |
30h | EPWM_TZFRC | Trip-zone Force Register | 0300 0030h | 0301 0030h | 0302 0030h |
32h | EPWM_ETSEL | Event Trigger Selection Register | 0300 0032h | 0301 0032h | 0302 0032h |
34h | EPWM_ETPS | Event Trigger Pre-Scale Register | 0300 0034h | 0301 0034h | 0302 0034h |
36h | EPWM_ETFLG | Event Trigger Flag Register | 0300 0036h | 0301 0036h | 0302 0036h |
38h | EPWM_ETCLR | Event Trigger Clear Register | 0300 0038h | 0301 0038h | 0302 0038h |
3Ah | EPWM_ETFRC | Event Trigger Force Register | 0300 003Ah | 0301 003Ah | 0302 003Ah |
3Ch | EPWM_PCCTL | PWM Chopper Control Register | 0300 003Ch | 0301 003Ch | 0302 003Ch |
5Ch | EPWM_PID | Revision Register | 0300 005Ch | 0301 005Ch | 0302 005Ch |
Offset | Acronym | Register Name | EHRPWM3_EPWM Physical Address | EHRPWM4_EPWM Physical Address | EHRPWM5_EPWM Physical Address |
---|---|---|---|---|---|
0h | EPWM_TBCTL | Time-Base Control Register | 0303 0000h | 0304 0000h | 0305 0000h |
2h | EPWM_TBSTS | Time-Base Status Register | 0303 0002h | 0304 0002h | 0305 0002h |
4h | HRPWM_TBPHSHR | Time-Base Phase High-Resolution PWM Register | 0303 0004h | 0304 0004h | 0305 0004h |
6h | EPWM_TBPHS | Time-Base Counter Phase Register | 0303 0006h | 0304 0006h | 0305 0006h |
8h | EPWM_TBCNT | Time-Base Counter Register | 0303 0008h | 0304 0008h | 0305 0008h |
Ah | EPWM_TBPRD | Time-Base Period Register | 0303 000Ah | 0304 000Ah | 0305 000Ah |
Eh | EPWM_CMPCTL | Counter-Compare Control Register | 0303 000Eh | 0304 000Eh | 0305 000Eh |
10h | HRPWM_CMPAHR | Counter-Compare A High-Resolution Register | 0303 0010h | 0304 0010h | 0305 0010h |
12h | EPWM_CMPA | Counter-Compare A Register | 0303 0012h | 0304 0012h | 0305 0012h |
14h | EPWM_CMPB | Counter-Compare B Register | 0303 0014h | 0304 0014h | 0305 0014h |
16h | EPWM_AQCTLA | Action Qualifier Control Register for Output A | 0303 0016h | 0304 0016h | 0305 0016h |
18h | EPWM_AQCTLB | Action Qualifier Control Register for Output B | 0303 0018h | 0304 0018h | 0305 0018h |
1Ah | EPWM_AQSFRC | Action Qualifier Software Force Register | 0303 001Ah | 0304 001Ah | 0305 001Ah |
1Ch | EPWM_AQCSFRC | Action Qualifier Continuous Software Force Register | 0303 001Ch | 0304 001Ch | 0305 001Ch |
1Eh | EPWM_DBCTL | Dead Band Generator Control Register | 0303 001Eh | 0304 001Eh | 0305 001Eh |
20h | EPWM_DBRED | Dead Band Generator Rising Edge Delay Count Register | 0303 0020h | 0304 0020h | 0305 0020h |
22h | EPWM_DBFED | Dead Band Generator Falling Edge Delay Count Register | 0303 0022h | 0304 0022h | 0305 0022h |
24h | EPWM_TZSEL | Trip-zone Select Register | 0303 0024h | 0304 0024h | 0305 0024h |
28h | EPWM_TZCTL | Trip-zone Control Register | 0303 0028h | 0304 0028h | 0305 0028h |
2Ah | EPWM_TZEINT | Trip-zone Enable Interrupt Register | 0303 002Ah | 0304 002Ah | 0305 002Ah |
2Ch | EPWM_TZFLG | Trip-zone Flag Register | 0303 002Ch | 0304 002Ch | 0305 002Ch |
2Eh | EPWM_TZCLR | Trip-zone Clear Register | 0303 002Eh | 0304 002Eh | 0305 002Eh |
30h | EPWM_TZFRC | Trip-zone Force Register | 0303 0030h | 0304 0030h | 0305 0030h |
32h | EPWM_ETSEL | Event Trigger Selection Register | 0303 0032h | 0304 0032h | 0305 0032h |
34h | EPWM_ETPS | Event Trigger Pre-Scale Register | 0303 0034h | 0304 0034h | 0305 0034h |
36h | EPWM_ETFLG | Event Trigger Flag Register | 0303 0036h | 0304 0036h | 0305 0036h |
38h | EPWM_ETCLR | Event Trigger Clear Register | 0303 0038h | 0304 0038h | 0305 0038h |
3Ah | EPWM_ETFRC | Event Trigger Force Register | 0303 003Ah | 0304 003Ah | 0305 003Ah |
3Ch | EPWM_PCCTL | PWM Chopper Control Register | 0303 003Ch | 0304 003Ch | 0305 003Ch |
5Ch | EPWM_PID | Revision Register | 0303 005Ch | 0304 005Ch | 0305 005Ch |
Offset | Acronym | Register Name | EHRPWM0_EHRPWM Physical Address | EHRPWM1_EHRPWM Physical Address | EHRPWM2_EHRPWM Physical Address |
---|---|---|---|---|---|
40h | HRPWM_HRCTL | High-Resolution Control Register | 0300 8040h | 0301 8040h | 0302 8040h |
Offset | Acronym | Register Name | EHRPWM3_EHRPWM Physical Address | EHRPWM4_EHRPWM Physical Address | EHRPWM5_EHRPWM Physical Address |
---|---|---|---|---|---|
40h | HRPWM_HRCTL | High-Resolution Control Register | 0303 8040h | 0304 8040h | 0305 8040h |
EPWM_TBCTL is shown in Figure 12-2655 and described in Table 12-5087.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0000h |
EHRPWM1_EPWM | 0301 0000h |
EHRPWM2_EPWM | 0302 0000h |
EHRPWM3_EPWM | 0303 0000h |
EHRPWM4_EPWM | 0304 0000h |
EHRPWM5_EPWM | 0305 0000h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FREE_SOFT | PHSDIR | CLKDIV | HSPCLKDIV | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-1h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HSPCLKDIV | SWFSYNC | SYNCOSEL | PRDLD | PHSEN | CTRMODE | ||
R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-3h | ||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | FREE_SOFT | R/W | 0h | Emulation Mode Bits These bits select the behavior of the EPWM time-base counter during emulation events. 0h: Stop after the next time-base counter increment or decrement 1h: Stop when counter completes a whole cycle 2h: Free run 3h: Free run |
13 | PHSDIR | R/W | 0h | Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (EPWM_TBCNT) will count after a synchronization event occurs and a new phase value is loaded from the phase (EPWM_TBPHS) register. This is irrespective of the direction of the counter before the synchronization event. In the up-count and down-count modes this bit is ignored. 0h: Count down after the synchronization event 1h: Count up after the synchronization event |
12-10 | CLKDIV | R/W | 0h | Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) 0h: /1 (default on reset) 1h: /2 2h: /4 3h: /8 4h: /16 5h: /32 6h: /64 7h: /128 |
9-7 | HSPCLKDIV | R/W | 1h | High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV). 0h: /1 1h: /2 (default on reset) 2h: /4 3h: /6 4h: /8 5h: /10 6h: /12 7h: /14 |
6 | SWFSYNC | R/W | 0h | Software Forced Synchronization Pulse 0h: Writing a 0h has no effect and reads always return a 0h. 1h: Writing a 1h forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the EPWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 0h. |
5-4 | SYNCOSEL | R/W | 0h | Synchronization Output Select These bits select the source of the EPWMxSYNCO signal. 0h: EPWMxSYNC 1h: TBCNT = 0: Time-base counter equal to zero (EPWM_TBCNT[15-0] TBCNT = 0000h) 2h: TBCNT = CMPB: Time-base counter equal to counter-compare B (EPWM_TBCNT[15-0] TBCNT = EPWM_CMPB[15-0] CMPB) 3h: Disable EPWMxSYNCO signal |
3 | PRDLD | R/W | 0h | Active Period Register Load From Shadow Register Select 0h: The period register (EPWM_TBPRD) is loaded from its shadow register when the time-base counter, EPWM_TBCNT[15-0] TBCNT, is equal to zero. A write or read to the EPWM_TBPRD register accesses the shadow register. 1h: Load the EPWM_TBPRD register immediately without using a shadow register. A write or read to the EPWM_TBPRD register directly accesses the active register. |
2 | PHSEN | R/W | 0h | Counter Register Load From Phase Register Enable 0h: Do not load the time-base counter (EPWM_TBCNT) from the time-base phase register (EPWM_TBPHS) 1h: Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit. |
1-0 | CTRMODE | R/W | 3h | Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0h: Up-count mode 1h: Down-count mode 2h: Up-down-count mode 3h: Stop-freeze counter operation (default on reset) |
EPWM_TBSTS is shown in Figure 12-2656 and described in Table 12-5089.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0002h |
EHRPWM1_EPWM | 0301 0002h |
EHRPWM2_EPWM | 0302 0002h |
EHRPWM3_EPWM | 0303 0002h |
EHRPWM4_EPWM | 0304 0002h |
EHRPWM5_EPWM | 0305 0002h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRMAX | SYNCI | CTRDIR | ||||
R-0h | R/W1C-0h | R/W1C-0h | R-0h | ||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R | 0h | Reserved |
2 | CTRMAX | R/W1C | 0h | Time-Base Counter Max Latched Status Bit 0h = Reading a 0h indicates the time-base counter never reached its maximum value. Writing a 0h will have no effect. 1h = Reading a 1h on this bit indicates that the time-base counter reached the max value - 0xFFFF. Writing a 1h to this bit will clear the latched event. |
1 | SYNCI | R/W1C | 0h | Input Synchronization Latched Status Bit 0h = Writing a 0h will have no effect. Reading a 0h indicates no external synchronization event has occurred. 1h = Reading a 1h on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI). Writing a 1h to this bit will clear the latched event. |
0 | CTRDIR | R | 0h | Time-Base Counter Direction Status Bit At reset, the counter is frozen, therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via the EPWM_TBCTL[1-0] CTRMODE bit field. 0h = Time-Base Counter is currently counting down 1h = Time-Base Counter is currently counting up |
EPWM_TBPHSHR is shown in Figure 12-2657 and described in Table 12-5091.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0004h |
EHRPWM1_EPWM | 0301 0004h |
EHRPWM2_EPWM | 0302 0004h |
EHRPWM3_EPWM | 0303 0004h |
EHRPWM4_EPWM | 0304 0004h |
EHRPWM5_EPWM | 0305 0004h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TBPHSH | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TBPHSH | R/W | 0h | Time-base phase high-resolution bits |
7-0 | RESERVED | R | 0h | Reserved |
EPWM_TBPHS is shown in Figure 12-2658 and described in Table 12-5093.
Return to Summary Table.
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension, otherwise, this location is reserved.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0006h |
EHRPWM1_EPWM | 0301 0006h |
EHRPWM2_EPWM | 0302 0006h |
EHRPWM3_EPWM | 0303 0006h |
EHRPWM4_EPWM | 0304 0006h |
EHRPWM5_EPWM | 0305 0006h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBPHS | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TBPHS | R/W | 0h | These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal: [a] If EPWM_TBCTL[PHSEN] = 0h, then the synchronization event is ignored and the time-base counter is not loaded with the phase [b] If EPWM_TBCTL[PHSEN] = 1h, then the time-base counter (EPWM_TBCNT) will be loaded with the phase (EPWM_TBPHS) when a synchronization event occurs The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization These bits set time-base counter phase of the
selected EPWM relative to the time-base that is supplying the
synchronization input signal. |
EPWM_TBCNT is shown in Figure 12-2659 and described in Table 12-5095.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0008h |
EHRPWM1_EPWM | 0301 0008h |
EHRPWM2_EPWM | 0302 0008h |
EHRPWM3_EPWM | 0303 0008h |
EHRPWM4_EPWM | 0304 0008h |
EHRPWM5_EPWM | 0305 0008h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBCNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TBCNT | R/W | 0h | Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed. |
EPWM_TBPRD is shown in Figure 12-2660 and described in Table 12-5097.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 000Ah |
EHRPWM1_EPWM | 0301 000Ah |
EHRPWM2_EPWM | 0302 000Ah |
EHRPWM3_EPWM | 0303 000Ah |
EHRPWM4_EPWM | 0304 000Ah |
EHRPWM5_EPWM | 0305 000Ah |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBPRD | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TBPRD | R/W | 0h | These bits determine the period of the time-base
counter. This sets the PWM frequency. Shadowing of this register
is enabled and disabled by the EPWM_TBCTL[3] PRDLD bit. By
default this register is shadowed. |
EPWM_CMPCTL is shown in Figure 12-2661 and described in Table 12-5099.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 000Eh |
EHRPWM1_EPWM | 0301 000Eh |
EHRPWM2_EPWM | 0302 000Eh |
EHRPWM3_EPWM | 0303 000Eh |
EHRPWM4_EPWM | 0304 000Eh |
EHRPWM5_EPWM | 0305 000Eh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SHDWBFULL | SHDWAFULL | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHDWBMODE | RESERVED | SHDWAMODE | LOADBMODE | LOADAMODE | ||
R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9 | SHDWBFULL | R | 0h | Counter-compare B (EPWM_CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0h = CMPB shadow FIFO not full yet 1h = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value. |
8 | SHDWAFULL | R | 0h | Counter-compare A (EPWM_CMPA) Shadow Register Full Status Flag. The flag bit is set when a 32-bit write to EPWM_CMPA:HRPWM_CMPAHR register or a 16-bit write to the EPWM_CMPA register is made. A 16-bit write to the HRPWM_CMPAHR register will not affect the flag. This bit self clears once a load-strobe occurs. 0h = CMPA shadow FIFO not full yet 1h = Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value |
7 | RESERVED | R | 0h | Reserved |
6 | SHDWBMODE | R/W | 0h | Counter-compare B (EPWM_CMPB) Register Operating Mode 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action. |
5 | RESERVED | R | 0h | Reserved |
4 | SHDWAMODE | R/W | 0h | Counter-compare A (EPWM_CMPA) Register Operating Mode 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action. |
3-2 | LOADBMODE | R/W | 0h | Active Counter-Compare B (EPWM_CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (EPWM_CMPCTL[6] SHDWBMODE = 1h). 0h = Load on EPWM_TBCNT[15-0] TBCNT = 0h: Time-base counter equal to zero (EPWM_TBCNT[15-0] TBCNT= 0000h) 1h = Load on EPWM_TBCNT[15-0] TBCNT = EPWM_TBPRD[15-0] TBPRD: Time-base counter equal to period (EPWM_TBCNT[15-0] TBCNT = EPWM_TBPRD[15-0] TBPRD) 2h = Load on either EPWM_TBCNT[15-0] TBCNT = 0 or EPWM_TBCNT[15-0] TBCNT = EPWM_TBPRD[15-0] TBPRD 3h = Freeze (no loads possible) |
1-0 | LOADAMODE | R/W | 0h | Active Counter-Compare A (EPWM_CMPA) Load From Shadow Select Mode This bit has no effect in immediate mode (EPWM_CMPCTL[4] SHDWAMODE = 1h). 0h = Load on TBCNT = 0h: Time-base counter equal to zero (EPWM_TBCNT[15-0] TBCNT = 0000h) 1h = Load on TBCNT = TBPRD: Time-base counter equal to period (EPWM_TBCNT[15-0] TBCNT= EPWM_TBPRD[15-0] TBPRD) 2h = Load on either EPWM_TBCNT[15-0] TBCNT = 0h or EPWM_TBCNT[15-0] TBCNT = EPWM_TBPRD[15-0] TBPRD 3h = Freeze (no loads possible) |
EPWM_CMPAHR is shown in Figure 12-2662 and described in Table 12-5101.
Return to Summary Table.
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this location is reserved.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0010h |
EHRPWM1_EPWM | 0301 0010h |
EHRPWM2_EPWM | 0302 0010h |
EHRPWM3_EPWM | 0303 0010h |
EHRPWM4_EPWM | 0304 0010h |
EHRPWM5_EPWM | 0305 0010h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMPAHR | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | CMPAHR | R/W | 0h | Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation: 1h to 255h. |
7-0 | RESERVED | R | 0h | Reserved |
EPWM_CMPA is shown in Figure 12-2663 and described in Table 12-5103.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0012h |
EHRPWM1_EPWM | 0301 0012h |
EHRPWM2_EPWM | 0302 0012h |
EHRPWM3_EPWM | 0303 0012h |
EHRPWM4_EPWM | 0304 0012h |
EHRPWM5_EPWM | 0305 0012h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPA | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | CMPA | R/W | 0h | The value in the active EPWM_CMPA register is continuously compared to the time-base counter (register EPWM_TBCNT). When the values are equal, the counter-compare module generates a "Time-Base counter equal to counter compare A" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the EPWM_AQCTLA and EPWM_AQCTLB registers. The actions that can be defined in the EPWM_AQCTLA and EPWM_AQCTLB registers include the following.(a) Do nothing the event is ignored. (b) Clear: Pull the EPWMxA and/or EPWMxB signal low. (c) Set: Pull the EPWMxA and/or EPWMxB signal high. (d) Toggle the EPWMxA and/or EPWMxB signal. Shadowing of this register is enabled and disabled by the EPWM_CMPCTL[4] SHDWAMODE bit. By default this register is shadowed. (a) If EPWM_CMPCTL[4] SHDWAMODE = 0h, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the EPWM_CMPCTL[1-0] LOADAMODE bit field determines which event will load the active register from the shadow register. (b) Before a write, the EPWM_CMPCTL[8] SHDWAFULL bit can be read to determine if the shadow register is currently full. (c) If EPWM_CMPCTL[4] SHDWAMODE = 1h, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. (d) In either mode, the active and shadow registers share the same memory map address. |
EPWM_CMPB is shown in Figure 12-2664 and described in Table 12-5105.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0014h |
EHRPWM1_EPWM | 0301 0014h |
EHRPWM2_EPWM | 0302 0014h |
EHRPWM3_EPWM | 0303 0014h |
EHRPWM4_EPWM | 0304 0014h |
EHRPWM5_EPWM | 0305 0014h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPB | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | CMPB | R/W | 0h | The value in the active EPWM_CMPB register is continuously compared to the time-base counter (register EPWM_TBCNT). When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare B" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the EPWM_AQCTLA and EPWM_AQCTLB registers. The actions that can be defined in the EPWM_AQCTLA and EPWM_AQCTLB registers include the following.(a) Do nothing, the event is ignored. (b) Clear: Pull the EPWMxA and/or EPWMxB signal low. (c) Set: Pull the EPWMxA and/or EPWMxB signal high. (d) Toggle the EPWMxA and/or EPWMxB signal. Shadowing of this register is enabled and disabled by the EPWM_CMPCTL[6] SHDWBMODE bit. By default this register is shadowed. (a) If EPWM_CMPCTL[6] SHDWBMODE = 0h, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the EPWM_CMPCTL[3-2] LOADBMODE bit field determines which event will load the active register from the shadow register: (b) Before a write, the EPWM_CMPCTL[9] SHDWBFULL bit can be read to determine if the shadow register is currently full. (c) If EPWM_CMPCTL[6] SHDWBMODE = 1h, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. (d) In either mode, the active and shadow registers share the same memory map address. |
EPWM_AQCTLA is shown in Figure 12-2665 and described in Table 12-5107.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0016h |
EHRPWM1_EPWM | 0301 0016h |
EHRPWM2_EPWM | 0302 0016h |
EHRPWM3_EPWM | 0303 0016h |
EHRPWM4_EPWM | 0304 0016h |
EHRPWM5_EPWM | 0305 0016h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CBD | CBU | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAD | CAU | PRD | ZRO | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-10 | CBD | R/W | 0h | Action when the Time-Base counter equals the active EPWM_CMPB register and the counter is decrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low |
9-8 | CBU | R/W | 0h | Action when the counter equals the active EPWM_CMPB register and the counter is incrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low |
7-6 | CAD | R/W | 0h | Action when the counter equals the active EPWM_CMPA register and the counter is decrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low |
5-4 | CAU | R/W | 0h | Action when the counter equals the active EPWM_CMPA register and the counter is incrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low |
3-2 | PRD | R/W | 0h | Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low |
1-0 | ZRO | R/W | 0h | Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low |
EPWM_AQCTLB is shown in Figure 12-2666 and described in Table 12-5109.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0018h |
EHRPWM1_EPWM | 0301 0018h |
EHRPWM2_EPWM | 0302 0018h |
EHRPWM3_EPWM | 0303 0018h |
EHRPWM4_EPWM | 0304 0018h |
EHRPWM5_EPWM | 0305 0018h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CBD | CBU | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAD | CAU | PRD | ZRO | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-10 | CBD | R/W | 0h | Action when the counter equals the active EPWM_CMPB register and the counter is decrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low |
9-8 | CBU | R/W | 0h | Action when the counter equals the active EPWM_CMPB register and the counter is incrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low |
7-6 | CAD | R/W | 0h | Action when the counter equals the active EPWM_CMPA register and the counter is decrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low |
5-4 | CAU | R/W | 0h | Action when the counter equals the active EPWM_CMPA register and the counter is incrementing. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low |
3-2 | PRD | R/W | 0h | Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low |
1-0 | ZRO | R/W | 0h | Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low |
EPWM_AQSFRC is shown in Figure 12-2667 and described in Table 12-5111.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 001Ah |
EHRPWM1_EPWM | 0301 001Ah |
EHRPWM2_EPWM | 0302 001Ah |
EHRPWM3_EPWM | 0303 001Ah |
EHRPWM4_EPWM | 0304 001Ah |
EHRPWM5_EPWM | 0305 001Ah |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RLDCSF | OTSFB | ACTSFB | OTSFA | ACTSFA | |||
R/W-0h | R/W1C-0h | R/W-0h | R/W1C-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7-6 | RLDCSF | R/W | 0h | EPWM_AQCSFRC Active Register Reload From Shadow Options |
5 | OTSFB | R/W1C | 0h | One-Time Software Forced Event on Output B 0h = Writing a 0h (zero) has no effect. Always reads back a 0h. This bit is auto cleared once a write to this register is complete, that is, a forced event is initiated. This is a one-shot forced event. It can be overridden by another subsequent event on output B. 1h = Initiates a single s/w forced event |
4-3 | ACTSFB | R/W | 0h | Action when One-Time Software Force B Is invoked 0h = Does nothing (action disabled) 1h = Clear (low) 2h = Set (high) 3h = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir) |
2 | OTSFA | R/W1C | 0h | One-Time Software Forced Event on Output A 0h = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 1h = Initiates a single software forced event. |
1-0 | ACTSFA | R/W | 0h | Action When One-Time Software Force A Is Invoked 0h = Does nothing (action disabled). 1h = Clear (low). 2h = Set (high). 3h = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir) |
EPWM_AQCSFRC is shown in Figure 12-2668 and described in Table 12-5113.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 001Ch |
EHRPWM1_EPWM | 0301 001Ch |
EHRPWM2_EPWM | 0302 001Ch |
EHRPWM3_EPWM | 0303 001Ch |
EHRPWM4_EPWM | 0304 001Ch |
EHRPWM5_EPWM | 0305 001Ch |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSFB | CSFA | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3-2 | CSFB | R/W | 0h | Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use the EPWM_AQSFRC[7-6] RLDCSF bit field. 0h = Forcing disabled, that is, has no effect 1h = Forces a continuous low on output B 2h = Forces a continuous high on output B 3h = Software forcing is disabled and has no effect |
1-0 | CSFA | R/W | 0h | Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0h = Forcing disabled, that is, has no effect 1h = Forces a continuous low on output A 2h = Forces a continuous high on output A 3h = Software forcing is disabled and has no effect |
EPWM_DBCTL is shown in Figure 12-2669 and described in Table 12-5115.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 001Eh |
EHRPWM1_EPWM | 0301 001Eh |
EHRPWM2_EPWM | 0302 001Eh |
EHRPWM3_EPWM | 0303 001Eh |
EHRPWM4_EPWM | 0304 001Eh |
EHRPWM5_EPWM | 0305 001Eh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN_MODE | POLSEL | OUT_MODE | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-6 | RESERVED | R | 0h | Reserved |
5-4 | IN_MODE | R/W | 0h | Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms, the default is EPWMxA In is the source for both falling and rising-edge delays. 0h = EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 1h = EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 2h = EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 3h = EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal. |
3-2 | POLSEL | R/W | 0h | Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that the EPWM_DBCTL[1-0] OUT_MODE = 0b11 and EPWM_DBCTL[5-4] IN_MODE = 0b00. Other enhanced modes are also possible, but not regarded as typical usage modes. 0h = Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 1h = Active low complementary (ALC) mode. EPWMxA is inverted. 2h = Active high complementary (AHC). EPWMxB is inverted. 3h = Active low (AL) mode. Both EPWMxA and EPWMxB are inverted. |
1-0 | OUT_MODE | R/W | 0h | Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0h = Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 1h = Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by the EPWM_DBCTL[5-4] IN_MODE bit field. 2h = Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by the EPWM_DBCTL[5-4] IN_MODE bit field. 3h = Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by the EPWM_DBCTL[5-4] IN_MODE bit field. |
EPWM_DBRED is shown in Figure 12-2670 and described in Table 12-5117.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0020h |
EHRPWM1_EPWM | 0301 0020h |
EHRPWM2_EPWM | 0302 0020h |
EHRPWM3_EPWM | 0303 0020h |
EHRPWM4_EPWM | 0304 0020h |
EHRPWM5_EPWM | 0305 0020h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DEL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEL | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9-0 | DEL | R/W | 0h | Rising Edge Delay Count. 10-bit counter. |
EPWM_DBFED is shown in Figure 12-2671 and described in Table 12-5119.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0022h |
EHRPWM1_EPWM | 0301 0022h |
EHRPWM2_EPWM | 0302 0022h |
EHRPWM3_EPWM | 0303 0022h |
EHRPWM4_EPWM | 0304 0022h |
EHRPWM5_EPWM | 0305 0022h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DEL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEL | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9-0 | DEL | R/W | 0h | Falling Edge Delay Count. 10-bit counter |
EPWM_TZSEL is shown in Figure 12-2672 and described in Table 12-5121.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0024h |
EHRPWM1_EPWM | 0301 0024h |
EHRPWM2_EPWM | 0302 0024h |
EHRPWM3_EPWM | 0303 0024h |
EHRPWM4_EPWM | 0304 0024h |
EHRPWM5_EPWM | 0305 0024h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OSHTN | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CBCN | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0h | Reserved |
13 | OSHT6 | R/W | 0h | Trip-zone 5 (TZ5) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. The one-shot trip condition remains latched until you clear the condition via the EPWM_TZCLR register. 0h: Disable TZ5 as a one-shot trip source for this EPWM module 1h: Enable TZ5 as a one-shot trip source for this EPWM module |
12 | OSHT5 | R/W | 0h | Trip-zone 4 (TZ4) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. The one-shot trip condition remains latched until you clear the condition via the EPWM_TZCLR register. 0h: Disable TZ4 as a one-shot trip source for this EPWM module 1h: Enable TZ4 as a one-shot trip source for this EPWM module |
11 | OSHT4 | R/W | 0h | Trip-zone 3 (TZ3) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. The one-shot trip condition remains latched until you clear the condition via the EPWM_TZCLR register. 0h: Disable TZ3 as a one-shot trip source for this EPWM module 1h: Enable TZ3 as a one-shot trip source for this EPWM module |
10 | OSHT3 | R/W | 0h | Trip-zone 2 (TZ2) Select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. The one-shot trip condition remains latched until you clear the condition via the EPWM_TZCLR register. 0h: Disable TZ2 as a one-shot trip source for this EPWM module 1h: Enable TZ2 as a one-shot trip source for this EPWM module |
9 | OSHT2 | R/W | 0h | Trip-zone 1 (TZ1) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. The one-shot trip condition remains latched until you clear the condition via the EPWM_TZCLR register. 0h: Disable TZ1 as a one-shot trip source for this EPWM module 1h: Enable TZ1 as a one-shot trip source for this EPWM module |
8 | OSHT1 | R/W | 0h | Trip-zone 0 (TZ0) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. The one-shot trip condition remains latched until you clear the condition via the EPWM_TZCLR register. 0h: Disable TZ0 as a one-shot trip source for this EPWM module 1h: Enable TZ0 as a one-shot trip source for this EPWM module |
7-6 | RESERVED | R | 0h | Reserved |
5 | CBC5 | R/W | 0h | Trip-zone 5 (TZ5) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. A cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero. 0h: Disable TZ5 as a CBC trip source for this EPWM module 1h: Enable TZ5 as a CBC trip source for this EPWM module |
4 | CBC4 | R/W | 0h | Trip-zone 4 (TZ4) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. A cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero. 0h: Disable TZ4 as a CBC trip source for this EPWM module 1h: Enable TZ4 as a CBC trip source for this EPWM module |
3 | CBC3 | R/W | 0h | Trip-zone 3 (TZ3) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. A cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero. 0h: Disable TZ3 as a CBC trip source for this EPWM module 1h: Enable TZ3 as a CBC trip source for this EPWM module |
2 | CBC2 | R/W | 0h | Trip-zone 2 (TZ2) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. A cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero. 0h: Disable TZ2 as a CBC trip source for this EPWM module 1h: Enable TZ2 as a CBC trip source for this EPWM module |
1 | CBC1 | R/W | 0h | Trip-zone 1 (TZ1) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. A cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero. 0h: Disable TZ1 as a CBC trip source for this EPWM module 1h: Enable TZ1 as a CBC trip source for this EPWM module |
0 | CBC0 | R/W | 0h | Trip-zone 0 (TZ0) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs, the action defined in the EPWM_TZCTL register is taken on the EPWMxA and EPWMxB outputs. A cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero. 0h: Disable TZ0 as a CBC trip source for this EPWM module 1h: Enable TZ0 as a CBC trip source for this EPWM module |
EPWM_TZCTL is shown in Figure 12-2673 and described in Table 12-5123.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0028h |
EHRPWM1_EPWM | 0301 0028h |
EHRPWM2_EPWM | 0302 0028h |
EHRPWM3_EPWM | 0303 0028h |
EHRPWM4_EPWM | 0304 0028h |
EHRPWM5_EPWM | 0305 0028h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TZB | TZA | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3-2 | TZB | R/W | 0h | When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the EPWM_TZSEL register. 0h = High impedance (EPWMxB = High-impedance state) 1h = Force EPWMxB to a high state 2h = Force EPWMxB to a low state 3h = Do nothing, no action is taken on EPWMxB. |
1-0 | TZA | R/W | 0h | When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the EPWM_TZSEL register. 0h = High impedance (EPWMxA = High-impedance state) 1h = Force EPWMxA to a high state 2h = Force EPWMxA to a low state 3h = Do nothing, no action is taken on EPWMxA. |
EPWM_TZEINT is shown in Figure 12-2674 and described in Table 12-5125.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 002Ah |
EHRPWM1_EPWM | 0301 002Ah |
EHRPWM2_EPWM | 0302 002Ah |
EHRPWM3_EPWM | 0303 002Ah |
EHRPWM4_EPWM | 0304 002Ah |
EHRPWM5_EPWM | 0305 002Ah |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OST | CBC | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R | 0h | Reserved |
2 | OST | R/W | 0h | Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation |
1 | CBC | R/W | 0h | Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation 1h = Enable interrupt generation |
0 | RESERVED | R | 0h | Reserved |
EPWM_TZFLG is shown in Figure 12-2675 and described in Table 12-5127.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 002Ch |
EHRPWM1_EPWM | 0301 002Ch |
EHRPWM2_EPWM | 0302 002Ch |
EHRPWM3_EPWM | 0303 002Ch |
EHRPWM4_EPWM | 0304 002Ch |
EHRPWM5_EPWM | 0305 002Ch |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OST | CBC | INT | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R | 0h | Reserved |
2 | OST | R | 0h | Latched Status Flag for A One-Shot Trip Event 0h = No one-shot trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the EPWM_TZCLR register. |
1 | CBC | R | 0h | Latched Status Flag for Cycle-By-Cycle Trip Event 0h = No cycle-by-cycle trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The EPWM_TZFLG[1] CBC bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the pins is automatically cleared when the EPWM time-base counter reaches zero (EPWM_TBCNT[15-0] TBCNT = 0000h) if the trip condition is no longer present. The condition on the pins is only cleared when the TBCNT = 0000h no matter where in the cycle the CBC flag is cleared. This bit is cleared by writing the appropriate value to the EPWM_TZCLR register. |
0 | INT | R | 0h | Latched Trip Interrupt Status Flag 0h = Indicates no interrupt has been generated 1h = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the EPWM_TZCLR register. |
EPWM_TZCLR is shown in Figure 12-2676 and described in Table 12-5129.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 002Eh |
EHRPWM1_EPWM | 0301 002Eh |
EHRPWM2_EPWM | 0302 002Eh |
EHRPWM3_EPWM | 0303 002Eh |
EHRPWM4_EPWM | 0304 002Eh |
EHRPWM5_EPWM | 0305 002Eh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OST | CBC | INT | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R | 0h | Reserved |
2 | OST | R/W | 0h | Clear Flag for One-Shot Trip (OST) Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition |
1 | CBC | R/W | 0h | Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition |
0 | INT | R/W | 0h | Global Interrupt Clear Flag 0h = Has no effect. Always reads back a 0h 1h = Clears the trip-interrupt flag for this EPWM module (EPWM_TZFLG[0] INT) Note: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the EPWM_TZFLG[0] INT bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. |
EPWM_TZFRC is shown in Figure 12-2677 and described in Table 12-5131.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0030h |
EHRPWM1_EPWM | 0301 0030h |
EHRPWM2_EPWM | 0302 0030h |
EHRPWM3_EPWM | 0303 0030h |
EHRPWM4_EPWM | 0304 0030h |
EHRPWM5_EPWM | 0305 0030h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OST | CBC | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R | 0h | Reserved |
2 | OST | R/W | 0h | Force a One-Shot Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a one-shot trip event and sets the EPWM_TZFLG[2] OST bit. |
1 | CBC | R/W | 0h | Force a Cycle-by-Cycle Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a cycle-by-cycle trip event and sets the EPWM_TZFLG[1] CBC bit. |
0 | RESERVED | R | 0h | Reserved |
EPWM_ETSEL is shown in Figure 12-2678 and described in Table 12-5133.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0032h |
EHRPWM1_EPWM | 0301 0032h |
EHRPWM2_EPWM | 0302 0032h |
EHRPWM3_EPWM | 0303 0032h |
EHRPWM4_EPWM | 0304 0032h |
EHRPWM5_EPWM | 0305 0032h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTEN | INTSEL | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SOCB | R/W | 0h | Enable SOCB pulse when set to 1h. |
14-12 | SOCBSEL | R/W | 0h | EPWMxSOCB Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event) 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event) 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event) 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event) |
11 | SOCA | R/W | 0h | Enable SOCA pulse when set to 1h. |
10-8 | SOCASEL | R/W | 0h | EPWMxSOCA Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event) 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event) 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event) 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event) |
7-4 | RESERVED | R | 0h | Reserved |
3 | INTEN | R/W | 0h | Enable EPWM Interrupt (EPWMx_INT) Generation 0h: Disable EPWMx_INT generation 1h: Enable EPWMx_INT generation |
2-0 | INTSEL | R/W | 0h | EPWM Interrupt (EPWMx_INT) Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero. (EPWM_TBCNT = 0000h) 2h: Enable event time-base counter equal to period (EPWM_TBCNT = EPWM_TBPRD) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing 5h: Enable event time-base counter equal to CMPA when the timer is decrementing 6h: Enable event time-base counter equal to CMPB when the timer is incrementing 7h: Enable event time-base counter equal to CMPB when the timer is decrementing |
EPWM_ETPS is shown in Figure 12-2679 and described in Table 12-5135.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0034h |
EHRPWM1_EPWM | 0301 0034h |
EHRPWM2_EPWM | 0302 0034h |
EHRPWM3_EPWM | 0303 0034h |
EHRPWM4_EPWM | 0304 0034h |
EHRPWM5_EPWM | 0305 0034h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTCNT | INTPRD | |||||
R-0h | R-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | SOCBCNT | R | 0h | EPWMxSOCB Counter Register These bits indicate how many selected events have occurred. |
13-12 | SOCBPRD | R/W | 0h | EPWMxSOCB Period Select These bits select how many selected event need to occur before an SOCB pulse is generated. |
11-10 | SOCACNT | R | 0h | EPWMxSOCA Counter Register These bits indicate how many selected events have occurred. |
9-8 | SOCAPRD | R/W | 0h | EPWMxSOCA Period Select These bits select how many selected event need to occur before an SOCA pulse is generated. |
7-4 | RESERVED | R | 0h | Reserved |
3-2 | INTCNT | R | 0h | EPWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected EPWM_ETSEL[2-0] INTSEL events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, EPWM_ETSEL[0] INT = 0h or the interrupt flag is set, EPWM_ETFLG[0] INT = 1h, the counter will stop counting events when it reaches the period value EPWM_ETPS[3-2] INTCNT = EPWM_ETPS[1-0] INTPRD. 0h: No events have occurred 1h: 1 event has occurred 2h: 2 events have occurred 3h: 3 events have occurred |
1-0 | INTPRD | R/W | 0h | EPWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected EPWM_ETSEL[2-0] INTSEL events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled (EPWM_ETSEL[0] INT = 1h). If the interrupt status flag is set from a previous interrupt (EPWM_ETFLG[0] INT = 1) then no interrupt will be generated until the flag is cleared via the EPWM_ETCLR[0] INT bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the EPWM_ETPS[3-2] INTCNT bits will automatically be cleared. Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear. Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented. 0h: Disable the interrupt event counter. No interrupt will be generated and the EPWM_ETFRC[0] INT bit is ignored. 1h: Generate an interrupt on the first event INTCNT = 0b01 (first event) 2h: Generate interrupt on the EPWM_ETPS[3-2] INTCNT = 0b10 (second event) 3h: Generate interrupt on the EPWM_ETPS[3-2] INTCNT = 0b11 (third event) |
EPWM_ETFLG is shown in Figure 12-2680 and described in Table 12-5137.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0036h |
EHRPWM1_EPWM | 0301 0036h |
EHRPWM2_EPWM | 0302 0036h |
EHRPWM3_EPWM | 0303 0036h |
EHRPWM4_EPWM | 0304 0036h |
EHRPWM5_EPWM | 0305 0036h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | SOCB | R | 0h | Latched SOCB Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB Note: Unlike the INT flag bit, the EPWMxSOCB output will continue to pulse even if the flag bit is set. |
2 | SOCA | R | 0h | Latched SOCA Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA Note: Unlike the INT flag bit, the EPWMxSOCA output will continue to pulse even if the flag bit is set. |
1 | RESERVED | R | 0h | Reserved |
0 | INT | R | 0h | Latched EPWM Interrupt (EPWMx_INT) Status Flag 0h: Indicates no event occurred. 1h: Indicates that an EPWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the EPWM_ETFLG[0] INT bit is still set. If an interrupt is pending, it will not be generated until after the EPWM_ETFLG[0] INT bit is cleared. |
EPWM_ETCLR is shown in Figure 12-2681 and described in Table 12-5139.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 0038h |
EHRPWM1_EPWM | 0301 0038h |
EHRPWM2_EPWM | 0302 0038h |
EHRPWM3_EPWM | 0303 0038h |
EHRPWM4_EPWM | 0304 0038h |
EHRPWM5_EPWM | 0305 0038h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | RESERVED | R | 0h | Reserved |
0 | INT | R | 0h | ePWM Interrupt [EPWMx_INT] Flag Clear Bit |
EPWM_ETFRC is shown in Figure 12-2682 and described in Table 12-5141.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 003Ah |
EHRPWM1_EPWM | 0301 003Ah |
EHRPWM2_EPWM | 0302 003Ah |
EHRPWM3_EPWM | 0303 003Ah |
EHRPWM4_EPWM | 0304 003Ah |
EHRPWM5_EPWM | 0305 003Ah |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | SOCB | R/W | 0h | SOCB Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[3] SOCB flag bit |
2 | SOCA | R/W | 0h | SOCA Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[2] SOCA flag bit |
1 | RESERVED | R | 0h | Reserved |
0 | INT | R/W | 0h | EPWM Interrupt (EPWMx_INT) Flag Clear Bit 0h: Writing a 0 has no effect. Always reads back a 0h. 1h: Writing 1 clears the EPWM_ETFLG[0] INT flag bit and enable further interrupts pulses to be generated. |
EPWM_PCCTL is shown in Figure 12-2683 and described in Table 12-5143.
Return to Summary Table.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 003Ch |
EHRPWM1_EPWM | 0301 003Ch |
EHRPWM2_EPWM | 0302 003Ch |
EHRPWM3_EPWM | 0303 003Ch |
EHRPWM4_EPWM | 0304 003Ch |
EHRPWM5_EPWM | 0305 003Ch |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHPDUTY | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHPFREQ | OSHTWTH | CHPEN | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-8 | CHPDUTY | R/W | 0h | Chopping Clock Duty Cycle 0h = Duty = 1/8 (12.5%) 1h = Duty = 2/8 (25.0%) 2h = Duty = 3/8 (37.5%) 3h = Duty = 4/8 (50.0%) 4h = Duty = 5/8 (62.5%) 5h = Duty = 6/8 (75.0%) 6h = Duty = 7/8 (87.5%) 7h = Reserved |
7-5 | CHPFREQ | R/W | 0h | Chopping Clock Frequency 0h = Divide by 1 (no prescale) 1h = Divide by 2 2h = Divide by 3 3h = Divide by 4 4h = Divide by 5 5h = Divide by 6 6h = Divide by 7 7h = Divide by 8 |
4-1 | OSHTWTH | R/W | 0h | One-Shot Pulse Width 0h = 1 - SYSCLKOUT/8 wide 1h = 2 - SYSCLKOUT/8 wide 2h = 3 - SYSCLKOUT/8 wide 3h = 4 - SYSCLKOUT/8 wide Fh = 16 - SYSCLKOUT/8 wide |
0 | CHPEN | R/W | 0h | PWM-chopping Enable 0h = Disable (bypass) PWM chopping function 1h = Enable chopping function |
EPWM_HRCTL is shown in Figure 12-2684 and described in Table 12-5145.
Return to Summary Table.
This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension. Otherwise, this location is reserved.
Instance | Physical Address |
---|---|
EHRPWM0_EHRPWM | 0300 8040h |
EHRPWM1_EHRPWM | 0301 8040h |
EHRPWM2_EHRPWM | 0302 8040h |
EHRPWM3_EHRPWM | 0303 8040h |
EHRPWM4_EHRPWM | 0304 8040h |
EHRPWM5_EHRPWM | 0305 8040h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PULSESEL | DELBUSSEL | DELMODE | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | PULSESEL | R/W | 0h | Shadow Mode Bit Selects the time
event that loads the CMPAHR shadow value into the active
register. The user should select this event to match the selection of the CMPA load mode EPWM_CMPCTL[LOADMODE] bits in the EPWM module as follows. 0h: Load on CTR = 0. Time-base counter equal to zero (EPWM_TBCNT = 0000h). 1h: Load on CTR = PRD. Time-base counter equal to period (EPWM_TBCNT = TEPWM_TBPRD) 2h: Load on either CTR = 0 or CTR = PRD (should not be used with HRPWM) 3h: Freeze (No loads possible should not be used with HRPWM) 0h = CTR = PRD (counter equal period) 1h = CTR = 0 (counter equals zero) |
2 | DELBUSSEL | R/W | 0h | Control Mode Bits Selects the register (CMP or TBPHS) that controls the MEP. 0h = Select CMPAHR(8) register controls the edge position. This is duty control mode (default on reset). 1h = Select TBPHSHR(8) register controls the edge position (this is phase control mode). |
1-0 | DELMODE | R/W | 0h | Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic. 0h = HRPWM capability is disabled (default on reset) 1h = MEP control of rising edge 2h = MEP control of falling edge 3h = MEP control of both edges |
EPWM_PID is shown in Figure 12-2726 and described in Table 12-5147.
Return to Summary Table.
The revision register is used by software to track features, bugs, and compatibility.
Instance | Physical Address |
---|---|
EHRPWM0_EPWM | 0300 005Ch |
EHRPWM1_EPWM | 0301 005Ch |
EHRPWM2_EPWM | 0302 005Ch |
EHRPWM3_EPWM | 0303 005Ch |
EHRPWM4_EPWM | 0304 005Ch |
EHRPWM5_EPWM | 0305 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION | |||||||||||||||||||||||||||||||
44D10903h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REVISION | R | 44D10903h | TI Internal Data Identifies revision of peripheral. |