SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes CTRL_MMR0 and SEC_MMR0 integration in the device, including information about clocks, resets, and hardware requests.
One CTRL_MMR0 and one SEC_MMR0 modules are integrated in the device MAIN domain. Figure 5-333 shows their integration.
Table 5-682 through Table 5-684 summarize the integration of the CTRL_MMR0 and SEC_MMR0 modules in the device MAIN domain.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
CTRL_MMR0 SEC_MMR0 | PSC0 | PD0 | LPSC0 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
CTRL_MMR0 | CTRL_MMR0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | Functional and interface clock for the CTRL_MMR0 module with frequency equal to MAIN_SYSCLK0 divided by 4. |
SEC_MMR0 | SEC_MMR0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | Functional and interface clock for the SEC_MMR0 module with frequency equal to MAIN_SYSCLK0 divided by 4. |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
CTRL_MMR0 | CTRL_MMR0_RST | MOD_G_RST | LPSC0 | Module level main reset |
CTRL_MMR0_POR_RST | MOD_POR_RST | LPSC0 | Module power-on reset | |
SEC_MMR0 | SEC_MMR0_RST | MOD_G_RST | LPSC0 | SEC_MMR0 module reset |
Interrupt Requests | |||||
---|---|---|---|---|---|
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
CTRL_MMR0 | CTRL_MMR0_ACCESS_ERR_0 | GIC500_SPI_IN_780 | GIC500 | Interrupt indicating protection, addressing, lock violation. | Level |
MAIN2MCU_LVL_INTRTR0_IN_6 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_365 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_365 | R5FSS0_CORE1 | ||||
CTRL_MMR0_IPC_SET8_IPC_SET_IPCFG_0 | GIC500_PPI0_0_IN_16 | GIC500 | Interrupt generated by writing 1h to CTRLMMR_IPC_SET8[0]. | Level | |
CTRL_MMR0_IPC_SET9_IPC_SET_IPCFG_0 | GIC500_PPI0_1_IN_16 | GIC500 | Interrupt generated by writing 1h to CTRLMMR_IPC_SET9[0]. | Level | |
CTRL_MMR0_IPC_SET16_IPC_SET_IPCFG_0 | R5FSS0_CORE0_INTR_IN_0 | R5FSS0_CORE0 | Interrupt generated by writing 1h to CTRLMMR_IPC_SET16[0]. | Level | |
R5FSS0_CORE1_INTR_IN_0 | R5FSS0_CORE1 | ||||
CTRL_MMR0_IPC_SET17_IPC_SET_IPCFG_0 | R5FSS0_CORE0_INTR_IN_1 | R5FSS0_CORE0 | Interrupt generated by writing 1h to CTRLMMR_IPC_SET17[0]. | Level | |
R5FSS0_CORE1_INTR_IN_1 | R5FSS0_CORE1 | ||||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
CTRL_MMR0 | - | - | - | - | - |
For more information about CTRL_MMR0_ACCESS_ERR_0, see Section 5.1.3.3.1.3.
For more information about IPC_INTx, see Section 5.1.3.3.1.4.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.