SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are four GPIO modules integrated in the device MAIN domain - GPIO0, GPIO2, GPIO4, GPIO6. Figure 12-57 shows the integration of GPIO0, GPIO2, GPIO4, GPIO6.
Table 12-113 through Table 12-115 summarize the integration of GPIO0, GPIO2, GPIO4, GPIO6 in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
GPIO0 | PSC0 | PD0 | LPSC0 | CBASS0 |
GPIO2 | PSC0 | PD0 | LPSC9 | CBASS0 |
GPIO4 | PSC0 | PD0 | LPSC9 | CBASS0 |
GPIO6 | PSC0 | PD0 | LPSC9 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
GPIO0 | GPIO0_VBUS_CLK | SYSCLK0/4 | PLLCTRL0 | GPIO0 functional and interface clock |
GPIO2 | GPIO2_VBUS_CLK | SYSCLK0/4 | PLLCTRL0 | GPIO2 functional and interface clock |
GPIO4 | GPIO4_VBUS_CLK | SYSCLK0/4 | PLLCTRL0 | GPIO4 functional and interface clock |
GPIO6 | GPIO6_VBUS_CLK | SYSCLK0/4 | PLLCTRL0 | GPIO6 functional and interface clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
GPIO0 | GPIO0_RST | MOD_G_RST | LPSC0 | GPIO0 reset |
GPIO2 | GPIO2_RST | MOD_G_RST | LPSC9 | GPIO2 reset |
GPIO4 | GPIO4_RST | MOD_G_RST | LPSC9 | GPIO4 reset |
GPIO6 | GPIO6_RST | MOD_G_RST | LPSC9 | GPIO6 reset |
Interrupt Requests | ||||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type | |
GPIO0 | GPIO0_GPIO_[0:68] | GPIO0_VIRT_IN0_[0:68] | GPIO0_VIRT | GPIO0 pins [0:68] interrupt requests | Pulse | |
GPIO0_GPIO_BANK_0 | GPIOMUX_INTRTR0_IN_145 | GPIOMUX_INTRTR0 | GPIO0 bank0 interrupt request | Pulse | ||
GPIO0_GPIO_BANK_1 | GPIOMUX_INTRTR0_IN_146 | GPIOMUX_INTRTR0 | GPIO0 bank1 interrupt request | Pulse | ||
GPIO0_GPIO_BANK_2 | GPIOMUX_INTRTR0_IN_147 | GPIOMUX_INTRTR0 | GPIO0 bank2 interrupt request | Pulse | ||
GPIO0_GPIO_BANK_3 | GPIOMUX_INTRTR0_IN_148 | GPIOMUX_INTRTR0 | GPIO0 bank3 interrupt request | Pulse | ||
GPIO0_GPIO_BANK_4 | GPIOMUX_INTRTR0_IN_149 | GPIOMUX_INTRTR0 | GPIO0 bank4 interrupt request | Pulse | ||
GPIO2 | GPIO2_GPIO_[0:68] | GPIO0_VIRT_IN1_[0:68] | GPIO0_VIRT | GPIO2 pins [0:68] interrupt requests | Pulse | |
GPIO2_GPIO_BANK_0 | GPIOMUX_INTRTR0_IN_154 | GPIOMUX_INTRTR0 | GPIO2 bank0 interrupt request | Pulse | ||
GPIO2_GPIO_BANK_1 | GPIOMUX_INTRTR0_IN_155 | GPIOMUX_INTRTR0 | GPIO2 bank1 interrupt request | Pulse | ||
GPIO2_GPIO_BANK_2 | GPIOMUX_INTRTR0_IN_156 | GPIOMUX_INTRTR0 | GPIO2 bank2 interrupt request | Pulse | ||
GPIO2_GPIO_BANK_3 | GPIOMUX_INTRTR0_IN_157 | GPIOMUX_INTRTR0 | GPIO2 bank3 interrupt request | Pulse | ||
GPIO2_GPIO_BANK_4 | GPIOMUX_INTRTR0_IN_158 | GPIOMUX_INTRTR0 | GPIO2 bank4 interrupt request | Pulse | ||
GPIO4 | GPIO4_GPIO_[0:68] | GPIO0_VIRT_IN2_[0:68] | GPIO0_VIRT | GPIO4 pins [0:68] interrupt requests | Pulse | |
GPIO4_GPIO_BANK_0 | GPIOMUX_INTRTR0_IN_163 | GPIOMUX_INTRTR0 | GPIO4 bank0 interrupt request | Pulse | ||
GPIO4_GPIO_BANK_1 | GPIOMUX_INTRTR0_IN_164 | GPIOMUX_INTRTR0 | GPIO4 bank1 interrupt request | Pulse | ||
GPIO4_GPIO_BANK_2 | GPIOMUX_INTRTR0_IN_165 | GPIOMUX_INTRTR0 | GPIO4 bank2 interrupt request | Pulse | ||
GPIO4_GPIO_BANK_3 | GPIOMUX_INTRTR0_IN_166 | GPIOMUX_INTRTR0 | GPIO4 bank3 interrupt request | Pulse | ||
GPIO4_GPIO_BANK_4 | GPIOMUX_INTRTR0_IN_167 | GPIOMUX_INTRTR0 | GPIO4 bank4 interrupt request | Pulse | ||
GPIO6 | GPIO6_GPIO_[0:68] | GPIO0_VIRT_IN3_[0:68] | GPIO0_VIRT | GPIO6 pins [0:68] interrupt requests | Pulse | |
GPIO6_GPIO_BANK_0 | GPIOMUX_INTRTR0_IN_172 | GPIOMUX_INTRTR0 | GPIO6 bank0 interrupt request | Pulse | ||
GPIO6_GPIO_BANK_1 | GPIOMUX_INTRTR0_IN_173 | GPIOMUX_INTRTR0 | GPIO6 bank1 interrupt request | Pulse | ||
GPIO6_GPIO_BANK_2 | GPIOMUX_INTRTR0_IN_174 | GPIOMUX_INTRTR0 | GPIO6 bank2 interrupt request | Pulse | ||
GPIO6_GPIO_BANK_3 | GPIOMUX_INTRTR0_IN_175 | GPIOMUX_INTRTR0 | GPIO6 bank3 interrupt request | Pulse | ||
GPIO6_GPIO_BANK_4 | GPIOMUX_INTRTR0_IN_176 | GPIOMUX_INTRTR0 | GPIO6 bank4 interrupt request | Pulse |