SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The MCSPI_XFERLEVEL[15-8] AFL bit field is needed when the buffer is used to receive an MCSPI word from a peripheral (the MCSPI_CHCONF_0/1/2/3[28] FFER bit must be set to 1). It defines the almost-full buffer status. See Figure 12-341.
When the FIFO pointer reaches this level, an interrupt or a DMA request is sent to the processor to enable the system to read AFL + 1 bytes from the receive register.
AFL + 1 must correspond to a multiple value of the MCSPI_CHCONF_0/1/2/3[11-7] WL bit field.
When DMA is used, the request is de-asserted after the first receive register read.
No new request is asserted again as long as the system has not performed the correct number of read accesses.
The MCSPI_IRQSTATUS register bits are not available in DMA mode. In DMA mode, the MCSPI_DMA_READ_EVENTi request is asserted on the same conditions as the MCSPI_IRQSTATUS RXx_FULL flag.