SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The cycle length can be adjusted by writing the CPTS_NUDGE_REG_j[7:0] register value which is a two's complement value. A value of 0xFF will subtract one RCLK clock from the CPTS_LENGTH_REG_j[31:0] value. A value of 0x01 will add one RCLK clock to the CPTS_LENGTH_REG_j value. The CPTS_NUDGE_REG_j value is cleared to zero when the nudge has occurred.