SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3458 lists the PCIE_CORE_AXI registers. All register offset addresses not listed in Table 12-3458 should be considered as reserved locations and the register contents should not be modified.
PCIE core AXI configuration registers
Instance | Base Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 0000h |
Offset | Acronym | Register Name | PCIE1_CORE_DBN_CFG_PCIE_CORE Physical Address |
---|---|---|---|
00400000h + formula | PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0 | 0DC0 0000h + formula | |
00400004h + formula | PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1 | 0DC0 0004h + formula | |
00400008h + formula | PCIE_CORE_ATU_WRAPPER_OB_i_DESC0 | 0DC0 0008h + formula | |
0040000Ch + formula | PCIE_CORE_ATU_WRAPPER_OB_i_DESC1 | 0DC0 000Ch + formula | |
00400014h + formula | PCIE_CORE_ATU_WRAPPER_OB_i_DESC3 | 0DC0 0014h + formula | |
00400018h + formula | PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0 | 0DC0 0018h + formula | |
0040001Ch + formula | PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1 | 0DC0 001Ch + formula | |
00400400h + formula | PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0 | 0DC0 0400h + formula | |
00400404h + formula | PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1 | 0DC0 0404h + formula | |
00400408h + formula | PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0 | 0DC0 0408h + formula | |
0040040Ch + formula | PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1 | 0DC0 040Ch + formula | |
00400414h + formula | PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3 | 0DC0 0414h + formula | |
00400418h + formula | PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0 | 0DC0 0418h + formula | |
0040041Ch + formula | PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1 | 0DC0 041Ch + formula | |
00400800h + formula | PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0 | 0DC0 0800h + formula | |
00400804h + formula | PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1 | 0DC0 0804h + formula | |
00400820h | PCIE_CORE_ATU_CREDIT_THRESHOLD_C0 | 0DC0 0820h | |
00400824h | PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0 | 0DC0 0824h | |
00400840h + formula | PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0 | 0DC0 0840h + formula | |
00400844h + formula | PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1 | 0DC0 0844h + formula |
PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0 is shown in Figure 12-1757 and described in Table 12-3460.
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Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through
Offset = 400000h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | RSVD | NUM_BITS | |||||||||||||
R/W-0h | R-0h | R/W-0h | |||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | DATA | R/W | 0h | Bits [31:8] of PCIe Address Register for region N |
7-6 | RSVD | R | 0h | Bits 7 and 6 are reserved |
5-0 | NUM_BITS | R/W | 0h | Number_bits + 1 bits are passed through from AXI address to the PCIe address |
PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1 is shown in Figure 12-1758 and described in Table 12-3462.
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Provides bits 63:32 of the PCIe address
Offset = 400004h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Bits [63:32] of PCIe Address Register for region N |
PCIE_CORE_ATU_WRAPPER_OB_i_DESC0 is shown in Figure 12-1759 and described in Table 12-3464.
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Provides bits 31:0 of the Outbound PCIe Descriptor
Offset = 400008h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0008h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Lowest 32-bits of PCIe Descriptor Register for region N |
PCIE_CORE_ATU_WRAPPER_OB_i_DESC1 is shown in Figure 12-1760 and described in Table 12-3466.
Return to the Summary Table.
Provides bits 63:32 of the PCIe Descriptor
Offset = 40000Ch + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 000Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Lower middle 32-bits of PCIe Descriptor Register for region N |
PCIE_CORE_ATU_WRAPPER_OB_i_DESC3 is shown in Figure 12-1761 and described in Table 12-3468.
Return to the Summary Table.
Provides PASID Value and The present bit
Offset = 400014h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0014h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | DATA | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RSVD | R | 0h | reserved |
22-0 | DATA | R/W | 0h | {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit} |
PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0 is shown in Figure 12-1762 and described in Table 12-3470.
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holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability
Offset = 400018h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0018h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | RSVD | REGION_SIZE | |||||||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | DATA | R/W | 0h | Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region |
7-6 | RSVD | R/W | 0h | These needs to be forced to 0 |
5-0 | REGION_SIZE | R/W | 0h | the value programmed in this field + 1 gives the region size |
PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1 is shown in Figure 12-1763 and described in Table 12-3472.
Return to the Summary Table.
holds the base address [63:32] of this region.
Offset = 40001Ch + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 001Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Bits [63:32] of AXI outbound Base Address Register used to decode the region |
PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0 is shown in Figure 12-1764 and described in Table 12-3474.
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Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through
Offset = 400400h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0400h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | RSVD | NUM_BITS | |||||||||||||
R/W-0h | R-0h | R/W-0h | |||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | DATA | R/W | 0h | Bits [31:8] of PCIe Address Register for region N |
7-6 | RSVD | R | 0h | Bits 7 and 6 are reserved |
5-0 | NUM_BITS | R/W | 0h | Number_bits + 1 bits are passed through from AXI address to the PCIe address |
PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1 is shown in Figure 12-1765 and described in Table 12-3476.
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Provides bits 63:32 of the PCIe address
Offset = 400404h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0404h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Bits [63:32] of PCIe Address Register for region N |
PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0 is shown in Figure 12-1766 and described in Table 12-3478.
Return to the Summary Table.
Provides bits 31:0 of the Outbound PCIe Descriptor
Offset = 400408h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0408h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Lowest 32-bits of PCIe Descriptor Register for region N |
PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1 is shown in Figure 12-1767 and described in Table 12-3480.
Return to the Summary Table.
Provides bits 63:32 of the PCIe Descriptor
Offset = 40040Ch + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 040Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Lower middle 32-bits of PCIe Descriptor Register for region N |
PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3 is shown in Figure 12-1768 and described in Table 12-3482.
Return to the Summary Table.
Provides PASID Value and The present bit
Offset = 400414h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0414h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | DATA | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RSVD | R | 0h | reserved |
22-0 | DATA | R/W | 0h | {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit} |
PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0 is shown in Figure 12-1769 and described in Table 12-3484.
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Holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability
Offset = 400418h + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0418h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | RSVD | REGION_SIZE | |||||||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | DATA | R/W | 0h | Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region |
7-6 | RSVD | R/W | 0h | These needs to be forced to 0 |
5-0 | REGION_SIZE | R/W | 0h | the value programmed in this field + 1 gives the region size |
PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1 is shown in Figure 12-1770 and described in Table 12-3486.
Return to the Summary Table.
holds the base address [63:32] of this region.
Offset = 40041Ch + (i * 20h); where i = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 041Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Bits [63:32] of AXI outbound Base Address Register used to decode the region |
PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0 is shown in Figure 12-1771 and described in Table 12-3488.
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Provides bits 31:8 of the AXI Address and the number of PCIE address bits passed through
Offset = 400800h + (k * 8h); where k = 0h to 2h
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0800h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | RSVD0 | NUM_BITS | |||||||||||||
R/W-0h | R-0h | R/W-0h | |||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | DATA | R/W | 0h | Bits [31:8] of AXI Address Register for BAR N |
7-6 | RSVD0 | R | 0h | Bits 7 and 6 are reserved |
5-0 | NUM_BITS | R/W | 0h | The value programmed in this register +1 bits are passed through from PCIe to AXI |
PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1 is shown in Figure 12-1772 and described in Table 12-3490.
Return to the Summary Table.
Provides bits 63:32 of the AXI Address
Offset = 400804h + (k * 8h); where k = 0h to 2h
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0804h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Bits [63:32] of AXI Address Register for BAR N |
PCIE_CORE_ATU_CREDIT_THRESHOLD_C0 is shown in Figure 12-1773 and described in Table 12-3492.
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N/A
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0820h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HEADER | DATA | |||||||||||||||||||||||||||||
R/W-X | R/W-1h | R/W-10h | |||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-12 | HEADER | R/W | 1h | This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper |
11-0 | DATA | R/W | 10h | This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper |
PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0 is shown in Figure 12-1774 and described in Table 12-3494.
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N/A
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0824h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLEAR_LINK_DOWN_BIT_TO_PROCEED | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | CLEAR_LINK_DOWN_BIT_TO_PROCEED | R/W | 0h | This bit will be set when link down reset comes. client should clear this bit before issueing new traffic to the core |
PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0 is shown in Figure 12-1775 and described in Table 12-3496.
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Provides bits 31:0 of the AXI address
Offset = 400840h + (m * 40h) + (n * 8h); where m = 0 to 15h, n = 0h to 7h
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0840h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Bits [31:0] of Address Register for BAR N |
PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1 is shown in Figure 12-1776 and described in Table 12-3498.
Return to the Summary Table.
Provides bits 63:32 of the AXI address
Offset = 400844h + (m * 40h) + (n * 8h); where m = 0 to 15h, n = 0h to 7h
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0DC0 0844h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Bits [63:32] of AXI Address Register for BAR N |