SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 9-20 shows the MAIN2MCU_LVL_INTRTR0 integration.
Table 9-48 through Table 9-50 summarize the MAIN2MCU_LVL_INTRTR0 integration.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MAIN2MCU_LVL_INTRTR0 | PSC0 | PD0 | LPSC0 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MAIN2MCU_LVL_INTRTR0 | MAIN2MCU_LVL_INTRTR0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | Module functional and interface clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MAIN2MCU_LVL_INTRTR0 | MAIN2MCU_LVL_INTRTR0_RST | MOD_G_RST | LPSC0 | Module hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MAIN2MCU_LVL_INTRTR0 | MAIN2MCU_LVL_INTRTR0_OUTL_[63:0] | MCU_R5FSS0_INTR_IN_[223:160] | MCU_R5FSS0 | Module interrupt outputs [63:0] | Level |
Table 9-50 lists only the MAIN2MCU_LVL_INTRTR0 interrupt outputs. The mapping of interrupt sources to MAIN2MCU_LVL_INTRTR0 interrupt inputs is presented in Section 9.4.3.4.