SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The timesync event router (TIMESYNC_INTRTR0) and compare event router (CMPEVT_INTRTR0) are instantiations of the generic interrupt router module in the device.
The TIMESYNC_INTRTR0 implements a set of multiplexers to provide selection of active CPTS time sync events for routing to CPTS capable modules. There is one register per output that controls the selection (TIMESYNC_INTRTR0_MUXCNTL_y).
The CMPEVT_INTRTR0 implements a set of multiplexers to provide selection of active CPTS counter compare events for routing as CPU or DMA events. There is one register per output that controls the selection (CMPEVT_INTRTR0_MUXCNTL_y).
Table 11-114 summarizes the configuration details for TIMESYNC_INTRTR0 and CMPEVT_INTRTR0.
Module | Number of Inputs | Number of Outputs | Input Interrupt Type |
---|---|---|---|
TIMESYNC_INTRTR0 | 64 | 48 | Level |
CMPEVT_INTRTR0 | 15 | 15 | Pulse |
Refer to INTRTR Overview for the general programming sequence that is recommended to be followed for all interrupt routers in the device.