SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-592 lists the memory-mapped registers for the UDMASS_INTA0_CFG_IMAP. All register offset addresses not listed in Table 10-592 should be considered as reserved locations and the register contents should not be modified.
The Event to Interrupt Mapping Registers region is accessed by setting the cfg_rsel signal to 1 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_IMAP | 3094 0000h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP | 2856 0000h + formula |
Offset | Acronym | Register Name | NAVSS0_UDMASS_INTA0_CFG_IMAP Physical Address | MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP Physical Address |
---|---|---|---|---|
0h + formula | UDMA_INTA_IMAP_j | Interrupt Mapping Register | 3094 0000h + formula | 2856 0000h + formula |
UDMA_INTA_IMAP_j is shown in Figure 10-219 and described in Table 10-594.
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The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto.
Offset = 0h + (j * 8h); where
j = 0h to 11FFh for NAVSS0_UDMASS_INTA0_CFG_IMAP
j = 0h to 5FFh for MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_IMAP | 3094 0000h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP | 2856 0000h + formula |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 |
RESERVED | |||||||
R/W-X | |||||||
55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
RESERVED | |||||||
R/W-X | |||||||
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
RESERVED | |||||||
R/W-X | |||||||
39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | |||||||
R/W-X | |||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | REGNUM | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REGNUM | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BITNUM | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-17 | RESERVED | R/W | X | |
16-8 | REGNUM | R/W | 0h | Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in. |
7-6 | RESERVED | R/W | X | |
5-0 | BITNUM | R/W | 0h | Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in. |