SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Configure register submode TCR_TLR | see Table 12-765 | 0x7 |
Load the start and halt trigger value. | UART_TCR[7-4] AUTO_RTS_START | 0x- |
UART_TCR[3-0] AUTO_RTS_HALT | ||
Enable or disable receive and transmit hardware flow control mode. | UART_EFR[7] AUTO_CTS_EN | 0x- |
UART_EFR[6] AUTO_RTS_EN |