SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are seven DCC modules integrated in the device MAIN domain - DCC0 through DCC6. Figure 12-2922 shows the integration of DCC modules.
Table 12-5599 through Table 12-5601 summarize the integration of DCC in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
DCC0 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
DCC1 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
DCC2 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
DCC3 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
DCC4 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
DCC5 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
DCC6 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
DCC0 | DCC0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC0 interface and functional clock |
DCC1 | DCC1_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC1 interface and functional clock |
DCC2 | DCC2_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC2 interface and functional clock |
DCC3 | DCC3_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC3 interface and functional clock |
DCC4 | DCC4_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC4 interface and functional clock |
DCC5 | DCC5_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC5 interface and functional clock |
DCC6 | DCC6_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC6 interface and functional clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
DCC0 | DCC0_RST | MOD_G_RST | LPSC0 | DCC0 asynchronous module reset |
DCC1 | DCC1_RST | MOD_G_RST | LPSC0 | DCC1 asynchronous module reset |
DCC2 | DCC2_RST | MOD_G_RST | LPSC0 | DCC2 asynchronous module reset |
DCC3 | DCC3_RST | MOD_G_RST | LPSC0 | DCC3 asynchronous module reset |
DCC4 | DCC4_RST | MOD_G_RST | LPSC0 | DCC4 asynchronous module reset |
DCC5 | DCC5_RST | MOD_G_RST | LPSC0 | DCC5 asynchronous module reset |
DCC6 | DCC6_RST | MOD_G_RST | LPSC0 | DCC6 asynchronous module reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
DCC0 | DCC0_INTR_DONE_LEVEL_0 | GIC500_SPI_IN_328 | COMPUTE_CLUSTER0 | DCC0 one-shot mode complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_318 | R5FSS0_CORE0 | DCC0 one-shot mode complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_318 | R5FSS0_CORE1 | DCC0 one-shot mode complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_88 | MAIN2MCU_LVL_INTRTR0 | DCC0 one-shot mode complete interrupt | Level | ||
DCC0_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_104 | ESM0 | DCC0 error interrupt | Level | |
DCC1 | DCC1_INTR_DONE_LEVEL_0 | GIC500_SPI_IN_329 | COMPUTE_CLUSTER0 | DCC1 one-shot mode complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_319 | R5FSS0_CORE0 | DCC1 one-shot mode complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_319 | R5FSS0_CORE1 | DCC1 one-shot mode complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_89 | MAIN2MCU_LVL_INTRTR0 | DCC1 one-shot mode complete interrupt | Level | ||
DCC1_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_105 | ESM0 | DCC1 error interrupt | Level | |
DCC2 | DCC2_INTR_DONE_LEVEL_0 | GIC500_SPI_IN_330 | COMPUTE_CLUSTER0 | DCC2 one-shot mode complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_320 | R5FSS0_CORE0 | DCC2 one-shot mode complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_320 | R5FSS0_CORE1 | DCC2 one-shot mode complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_90 | MAIN2MCU_LVL_INTRTR0 | DCC2 one-shot mode complete interrupt | Level | ||
DCC2_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_106 | ESM0 | DCC2 error interrupt | Level | |
DCC3 | DCC3_INTR_DONE_LEVEL_0 | GIC500_SPI_IN_331 | COMPUTE_CLUSTER0 | DCC3 one-shot mode complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_321 | R5FSS0_CORE0 | DCC3 one-shot mode complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_321 | R5FSS0_CORE1 | DCC3 one-shot mode complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_91 | MAIN2MCU_LVL_INTRTR0 | DCC3 one-shot mode complete interrupt | Level | ||
DCC3_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_107 | ESM0 | DCC3 error interrupt | Level | |
DCC4 | DCC4_INTR_DONE_LEVEL_0 | GIC500_SPI_IN_332 | COMPUTE_CLUSTER0 | DCC4 one-shot mode complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_322 | R5FSS0_CORE0 | DCC4 one-shot mode complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_322 | R5FSS0_CORE1 | DCC4 one-shot mode complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_92 | MAIN2MCU_LVL_INTRTR0 | DCC4 one-shot mode complete interrupt | Level | ||
DCC4_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_108 | ESM0 | DCC4 error interrupt | Level | |
DCC5 | DCC5_INTR_DONE_LEVEL_0 | GIC500_SPI_IN_333 | COMPUTE_CLUSTER0 | DCC5 one-shot mode complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_323 | R5FSS0_CORE0 | DCC5 one-shot mode complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_323 | R5FSS0_CORE1 | DCC5 one-shot mode complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_93 | MAIN2MCU_LVL_INTRTR0 | DCC5 one-shot mode complete interrupt | Level | ||
DCC5_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_109 | ESM0 | DCC5 error interrupt | Level | |
DCC6 | DCC6_INTR_DONE_LEVEL_0 | GIC500_SPI_IN_334 | COMPUTE_CLUSTER0 | DCC6 one-shot mode complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_324 | R5FSS0_CORE0 | DCC6 one-shot mode complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_324 | R5FSS0_CORE1 | DCC6 one-shot mode complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_94 | MAIN2MCU_LVL_INTRTR0 | DCC6 one-shot mode complete interrupt | Level | ||
DCC6_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_110 | ESM0 | DCC6 error interrupt | Level |
Table 12-5602 through Table 12-5604 summarize the DCC input source clocks in the device MAIN domain.
DCCCLKSRC0 / DCCCLKSRC1 value: | DCC0 | DCC1 | DCC2 | |||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Input0 | Input1 | Input0 | Input1 | Input0 | Input1 | |||||||||||||||||||||||||||||||||||
MUX0 | MUX1 | MUX0 | MUX1 | MUX0 | MUX1 | |||||||||||||||||||||||||||||||||||
0-4, 6-9, B-F | A | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9-F | 0-4, 6-9, B-F | A | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9-F | 0-4, 6-9, B-F | A | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9-F | ||
Clock Source | Input: | CLOCK0[0] | CLOCK0[1] | CLOCK0[2] | CLOCK1 | CLKSRC0 | CLKSRC1 | CLKSRC2 | CLKSRC3 | CLKSRC4 | CLKSRC5 | CLKSRC6 | CLKSRC7 | FICLK | CLOCK0[0] | CLOCK0[1] | CLOCK0[2] | CLOCK1 | CLKSRC0 | CLKSRC1 | CLKSRC2 | CLKSRC3 | CLKSRC4 | CLKSRC5 | CLKSRC6 | CLKSRC7 | FICLK | CLOCK0[0] | CLOCK0[1] | CLOCK0[2] | CLOCK1 | CLKSRC0 | CLKSRC1 | CLKSRC2 | CLKSRC3 | CLKSRC4 | CLKSRC5 | CLKSRC6 | CLKSRC7 | FICLK |
HFOSC0_CLKOUT | External Reference Clock Input to WKUP/MCU | ✓ | ✓ | ✓ | ✓ | |||||||||||||||||||||||||||||||||||
HFOSC1_CLKOUT | External Reference Clock Input to MAIN | ✓ | ✓ | ✓ | ✓ | |||||||||||||||||||||||||||||||||||
CLK_12M_RC | Internal 12.5MHz RC oscillator (Always ON) | ✓ | ✓ | ✓ | ||||||||||||||||||||||||||||||||||||
MAIN PLLCTRL | ||||||||||||||||||||||||||||||||||||||||
MAIN_SYSCLK0 (CLK1) | CLK1 | ✓ | ||||||||||||||||||||||||||||||||||||||
CLK1/2 | CLK1/2 | ✓ | ||||||||||||||||||||||||||||||||||||||
CLK1/4 | CLK1/4 | ✓ | ✓ | ✓ | ✓ | ✓ | ||||||||||||||||||||||||||||||||||
MAIN_PLL0_CLKOUT (MAIN PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL0_HSDIV1_CLKOUT | DMTIMER Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL0_HSDIV2_CLKOUT | eMMCSD Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL0_HSDIV3_CLKOUT | GPMC Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL0_HSDIV4_CLKOUT | MCAN Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL0_HSDIV5_CLKOUT | SPI Reference clock | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL0_HSDIV6_CLKOUT | CPTS/IEP Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL0_HSDIV7_CLKOUT | ATL | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL1_CLKOUT (PER0 PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL1_HSDIV0_CLKOUT | MAIN UARTs; I2C | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL1_HSDIV1_CLKOUT | CPSW5X CPPI CLK | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL1_HSDIV2_CLKOUT | eMMCSD Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL1_HSDIV3_CLKOUT | DMTIMER Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL1_HSDIV7_CLKOUT | USB - LPM/SOF CLK | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL2_CLKOUT (PER1 PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL2_HSDIV1_CLKOUT_DIV2 | GPMC Clock Mux; DSS Functional Clock | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL2_HSDIV2_CLKOUT | eMMCSD Clock Mux; McASP/ATL clock mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL2_HSDIV4_CLKOUT | SerDes Reference Clock | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL2_HSDIV6_CLKOUT | DMTIMER Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL3_CLKOUT (CPSW9G PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL3_HSDIV0_CLKOUT | CPSW5XRGMII/GMII Clock | ✓ | ||||||||||||||||||||||||||||||||||||||
eDP0 REFCLK_OUT | SerDes Reference Clock Output | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL14_CLKOUT (PULSAR PLL) | ||||||||||||||||||||||||||||||||||||||||
CPTS_RFT_CLK | IO Reference clock input | ✓ |
DCCCLKSRC0 / DCCCLKSRC1 value: | DCC3 | DCC4 | DCC5 | |||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Input0 | Input1 | Input0 | Input1 | Input0 | Input1 | |||||||||||||||||||||||||||||||||||
MUX0 | MUX1 | MUX0 | MUX1 | MUX0 | MUX1 | |||||||||||||||||||||||||||||||||||
0-4, 6-9, B-F | A | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9-F | 0-4, 6-9, B-F | A | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9-F | 0-4, 6-9, B-F | A | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9-F | ||
Clock Source | Input: | CLOCK0[0] | CLOCK0[1] | CLOCK0[2] | CLOCK1 | CLKSRC0 | CLKSRC1 | CLKSRC2 | CLKSRC3 | CLKSRC4 | CLKSRC5 | CLKSRC6 | CLKSRC7 | FICLK | CLOCK0[0] | CLOCK0[1] | CLOCK0[2] | CLOCK1 | CLKSRC0 | CLKSRC1 | CLKSRC2 | CLKSRC3 | CLKSRC4 | CLKSRC5 | CLKSRC6 | CLKSRC7 | FICLK | CLOCK0[0] | CLOCK0[1] | CLOCK0[2] | CLOCK1 | CLKSRC0 | CLKSRC1 | CLKSRC2 | CLKSRC3 | CLKSRC4 | CLKSRC5 | CLKSRC6 | CLKSRC7 | FICLK |
HFOSC0_CLKOUT | External Reference Clock Input to WKUP/MCU | ✓ | ✓ | ✓ | ||||||||||||||||||||||||||||||||||||
HFOSC1_CLKOUT | External Reference Clock Input to MAIN | ✓ | ✓ | ✓ | ||||||||||||||||||||||||||||||||||||
CLK_12M_RC | Internal 12.5MHz RC oscillator (Always ON) | ✓ | ✓ | ✓ | ||||||||||||||||||||||||||||||||||||
MAIN PLLCTRL | ||||||||||||||||||||||||||||||||||||||||
MAIN_SYSCLK0 (CLK1) | CLK1 | ✓ | ||||||||||||||||||||||||||||||||||||||
CLK1/2 | CLK1/2 | ✓ | ||||||||||||||||||||||||||||||||||||||
CLK1/4 | CLK1/4 | ✓ | ✓ | ✓ | ✓ | |||||||||||||||||||||||||||||||||||
MAIN_PLL3_CLKOUT (CPSW9G PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL3_HSDIV3_CLKOUT | DMTIMER Clock Mux | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL3_HSDIV4_CLKOUT | SerDes Reference Clock | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL4_CLKOUT (AUDIO0 PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL4_HSDIV0_CLKOUT | McASP; some multiple of Audio Sampling rate | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL4_HSDIV1_CLKOUT | ATL | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL4_HSDIV2_CLKOUT | DMTIMERS | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL7_CLKOUT (C7x PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL7_HSDIV0_CLKOUT_DIV4 | MSMC | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL8_CLKOUT (ARM0 PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL8_HSDIV0_CLKOUT_DIV8 | ARM0 Core | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL12_CLKOUT (DDR PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL12_HSDIV0_CLKOUT_DIV4 | DDR | ✓ | ||||||||||||||||||||||||||||||||||||||
MAIN_PLL14_CLKOUT (PULSAR PLL) | ||||||||||||||||||||||||||||||||||||||||
MAIN_PLL14_HSDIV0_CLKOUT_DIV4 | Main Pulsar1 | ✓ | ||||||||||||||||||||||||||||||||||||||
GPMC_CLK | IO Clock input in Slave mode | ✓ | ||||||||||||||||||||||||||||||||||||||
AUDIO_EXT_REFCLK0 | IO Clock input in Slave mode | ✓ | ||||||||||||||||||||||||||||||||||||||
AUDIO_EXT_REFCLK1 | IO Clock input in Slave mode | ✓ | ||||||||||||||||||||||||||||||||||||||
CLK_32K | 32KHz Clock (from WKUP domain) | ✓ | ||||||||||||||||||||||||||||||||||||||
LFXOSC_CLKOUT | 32.768KHz external clock (from WKUP domain) | ✓ | ||||||||||||||||||||||||||||||||||||||
MCU_EXT_REFCLK0 | External Ref clock from WKUP domain | ✓ | ||||||||||||||||||||||||||||||||||||||
RMII1_REFCLK | IO Reference clock input | ✓ | ||||||||||||||||||||||||||||||||||||||
RGMII1_RXC | IO Receive clock input | ✓ | ||||||||||||||||||||||||||||||||||||||
RGMII2_RXC | IO Receive clock input | ✓ | ||||||||||||||||||||||||||||||||||||||
RGMII3_RXC | IO Receive clock input | ✓ | ||||||||||||||||||||||||||||||||||||||
RGMII4_RXC | IO Receive clock input | ✓ |
DCCCLKSRC0 / DCCCLKSRC1 value: | DCC6 | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Input0 | Input1 | |||||||||||||
MUX0 | MUX1 | |||||||||||||
0-4, 6-9, B-F | A | 5 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9-F | ||
Clock Source | Input: | CLOCK0[0] | CLOCK0[1] | CLOCK0[2] | CLOCK1 | CLKSRC0 | CLKSRC1 | CLKSRC2 | CLKSRC3 | CLKSRC4 | CLKSRC5 | CLKSRC6 | CLKSRC7 | FICLK |
HFOSC0_CLKOUT | External Reference Clock Input to WKUP/MCU | ✓ | ||||||||||||
HFOSC1_CLKOUT | External Reference Clock Input to MAIN | ✓ | ||||||||||||
CLK_12M_RC | Internal 12.5MHz RC oscillator (Always ON) | ✓ | ||||||||||||
MAIN PLLCTRL | ||||||||||||||
MAIN_SYSCLK0/4 | CLK1/4 | ✓ | ✓ | |||||||||||
MAIN_PLL3_CLKOUT (CPSW9G PLL) | ||||||||||||||
MAIN_PLL3_HSDIV1_CLKOUT | CPTS/IEP Clock Mux, ICSS Core clock Mux | ✓ | ||||||||||||
MAIN_PLL3_HSDIV2_CLKOUT | eMMCSD Clock Mux | ✓ | ||||||||||||
MAIN_PLL14_CLKOUT (PULSAR PLL) | ||||||||||||||
MCASP0_ACLKX | IO Clock input in Slave mode | ✓ | ||||||||||||
MCASP0_ACLKR | IO Clock input in Slave mode | ✓ | ||||||||||||
MCASP1_ACLKX | IO Clock input in Slave mode | ✓ | ||||||||||||
MCASP1_ACLKR | IO Clock input in Slave mode | ✓ | ||||||||||||
MCASP2_ACLKX | IO Clock input in Slave mode | ✓ | ||||||||||||
MCASP2_ACLKR | IO Clock input in Slave mode | ✓ |