SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
A prescaler can be used to divide the timer counter input clock frequency. The prescaler is enabled when the TIMER_TCLR[5] PRE bit is set. The TIMER_TCLR[4-2] PTV bit field sets the 2n division ratio (prescaler value is 2(PTV + 1). The prescaler counter is reset when the timer counter is stopped or reloaded on-the-fly.
Table 12-5527 lists the prescaler/timer reload values versus contexts.
Context | Prescaler | Timer Counter |
---|---|---|
Overflow (when autoreload is on) | Reset | TIMER_TLDR[31-0] |
TIMER_TCRR write | Reset | TIMER_TCRR[31-0] |
TIMER_TTGR write | Reset | TIMER_TLDR[31-0] |
Stop | Reset | Frozen |