SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Interrupt Input Line | Interrupt ID | Interrupt Name |
---|---|---|
ESM0_LVL_IN_0 | 0 | PLLFRAC2_SSMOD0_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_1 | 1 | PLLFRAC2_SSMOD1_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_2 | 2 | PLLFRAC2_SSMOD2_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_3 | 3 | PLLFRAC2_SSMOD3_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_4 | 4 | PLLFRAC2_SSMOD4_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_7 | 7 | PLLFRACF_SSMOD7_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_8 | 8 | PLLFRACF_SSMOD8_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_12 | 12 | PLLFRACF_SSMOD12_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_14 | 14 | PLLFRAC2_SSMOD14_LOCKLOSS_IPCFG_0 |
ESM0_LVL_IN_32 | 32 | DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_NONFATAL_0 |
ESM0_LVL_IN_33 | 33 | DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_FATAL_0 |
ESM0_LVL_IN_34 | 34 | DDR0_DDRSS_HS_PHY_GLOBAL_ERROR_0 |
ESM0_LVL_IN_40 | 40 | A72SS0_CORE0_INTERRIRQ_0 |
ESM0_LVL_IN_41 | 41 | A72SS0_CORE0_EXTERRIRQ_0 |
ESM0_LVL_IN_48 | 48 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_0 |
ESM0_LVL_IN_49 | 49 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_1 |
ESM0_LVL_IN_50 | 50 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_2 |
ESM0_LVL_IN_51 | 51 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_3 |
ESM0_LVL_IN_52 | 52 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_4 |
ESM0_LVL_IN_53 | 53 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_5 |
ESM0_LVL_IN_54 | 54 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_6 |
ESM0_LVL_IN_55 | 55 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_7 |
ESM0_LVL_IN_56 | 56 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_8 |
ESM0_LVL_IN_57 | 57 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_9 |
ESM0_LVL_IN_58 | 58 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_10 |
ESM0_LVL_IN_59 | 59 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_11 |
ESM0_LVL_IN_60 | 60 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_12 |
ESM0_LVL_IN_61 | 61 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_13 |
ESM0_LVL_IN_62 | 62 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_14 |
ESM0_LVL_IN_63 | 63 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_15 |
ESM0_LVL_IN_64 | 64 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_16 |
ESM0_LVL_IN_65 | 65 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_17 |
ESM0_LVL_IN_66 | 66 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_18 |
ESM0_LVL_IN_67 | 67 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_19 |
ESM0_LVL_IN_68 | 68 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_20 |
ESM0_LVL_IN_69 | 69 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_39 |
ESM0_LVL_IN_70 | 70 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_40 |
ESM0_LVL_IN_71 | 71 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_41 |
ESM0_LVL_IN_72 | 72 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_46 |
ESM0_LVL_IN_73 | 73 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_47 |
ESM0_LVL_IN_74 | 74 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_48 |
ESM0_LVL_IN_75 | 75 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_62 |
ESM0_LVL_IN_76 | 76 | COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_63 |
ESM0_LVL_IN_103 | 103 | COMPUTE_CLUSTER0_MSMC_EN_EN_SNOOP_TIMED_OUT_INTR0_0 |
ESM0_LVL_IN_104 | 104 | DCC0_INTR_ERR_LEVEL_0 |
ESM0_LVL_IN_105 | 105 | DCC1_INTR_ERR_LEVEL_0 |
ESM0_LVL_IN_106 | 106 | DCC2_INTR_ERR_LEVEL_0 |
ESM0_LVL_IN_107 | 107 | DCC3_INTR_ERR_LEVEL_0 |
ESM0_LVL_IN_108 | 108 | DCC4_INTR_ERR_LEVEL_0 |
ESM0_LVL_IN_109 | 109 | DCC5_INTR_ERR_LEVEL_0 |
ESM0_LVL_IN_110 | 110 | DCC6_INTR_ERR_LEVEL_0 |
ESM0_LVL_IN_120 | 120 | PDMA5_ECC_SEC_PEND_0 |
ESM0_LVL_IN_121 | 121 | PDMA5_ECC_DED_PEND_0 |
ESM0_LVL_IN_124 | 124 | USB0_ASF_INT_NONFATAL_0 |
ESM0_LVL_IN_125 | 125 | USB0_ASF_INT_FATAL_0 |
ESM0_LVL_IN_126 | 126 | USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_127 | 127 | USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_140 | 140 | MCAN16_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_141 | 141 | MCAN16_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_142 | 142 | MCAN17_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_143 | 143 | MCAN17_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_152 | 152 | I3C0_PCLK_ECC_UNCORR_LVL_0 |
ESM0_LVL_IN_153 | 153 | I3C0_SCLK_ECC_UNCORR_LVL_0 |
ESM0_LVL_IN_154 | 154 | I3C0_I3C_NONFATAL__INT_0 |
ESM0_LVL_IN_155 | 155 | I3C0_I3C_FATAL__INT_0 |
ESM0_LVL_IN_160 | 160 | NAVSS0_MODSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_161 | 161 | NAVSS0_MODSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_162 | 162 | NAVSS0_UDMASS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_163 | 163 | NAVSS0_UDMASS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_164 | 164 | NAVSS0_NBSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_165 | 165 | NAVSS0_NBSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_166 | 166 | NAVSS0_VIRTSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_167 | 167 | NAVSS0_VIRTSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
ESM0_LVL_IN_170 | 170 | MSRAM_512K0_ECC_CORR_LEVEL_0 |
ESM0_LVL_IN_171 | 171 | MSRAM_512K0_ECC_UNCORR_LEVEL_0 |
ESM0_LVL_IN_172 | 172 | PSRAMECC0_ECC_CORR_LEVEL_0 |
ESM0_LVL_IN_173 | 173 | PSRAMECC0_ECC_UNCORR_LEVEL_0 |
ESM0_LVL_IN_174 | 174 | PSRAM2KECC0_ECC_CORR_LEVEL_0 |
ESM0_LVL_IN_175 | 175 | PSRAM2KECC0_ECC_UNCORR_LEVEL_0 |
ESM0_LVL_IN_176 | 176 | MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0 |
ESM0_LVL_IN_177 | 177 | MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_178 | 178 | MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0 |
ESM0_LVL_IN_179 | 179 | MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_180 | 180 | MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0 |
ESM0_LVL_IN_181 | 181 | MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_182 | 182 | MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0 |
ESM0_LVL_IN_183 | 183 | MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_188 | 188 | R5FSS0_COMMON0_ECC_SE_TO_ESM_0_0 |
ESM0_LVL_IN_189 | 189 | R5FSS0_COMMON0_ECC_DE_TO_ESM_0_0 |
ESM0_LVL_IN_190 | 190 | R5FSS0_COMMON0_ECC_SE_TO_ESM_1_0 |
ESM0_LVL_IN_191 | 191 | R5FSS0_COMMON0_ECC_DE_TO_ESM_1_0 |
ESM0_LVL_IN_292 | 292 | DDR0_DDRSS_CFG_ECC_AGGR_CORR_ERR_LVL_0 |
ESM0_LVL_IN_293 | 293 | DDR0_DDRSS_CFG_ECC_AGGR_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_294 | 294 | DDR0_DDRSS_CTL_ECC_AGGR_CORR_ERR_LVL_0 |
ESM0_LVL_IN_295 | 295 | DDR0_DDRSS_CTL_ECC_AGGR_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_296 | 296 | DDR0_DDRSS_VBUS_ECC_AGGR_CORR_ERR_LVL_0 |
ESM0_LVL_IN_297 | 297 | DDR0_DDRSS_VBUS_ECC_AGGR_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_298 | 298 | DDR0_DDRSS_DRAM_ECC_CORR_ERR_LVL_0 |
ESM0_LVL_IN_299 | 299 | DDR0_DDRSS_DRAM_ECC_UNCORR_ERR_LVL_0 |
ESM0_LVL_IN_306 | 306 | CPSW0_ECC_SEC_PEND_0 |
ESM0_LVL_IN_307 | 307 | CPSW0_ECC_DED_PEND_0 |
ESM0_LVL_IN_308 | 308 | SERDES_10G1_PHY_PWR_TIMEOUT_LVL_0 |
ESM0_LVL_IN_312 | 312 | MCAN0_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_313 | 313 | MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_314 | 314 | MCAN1_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_315 | 315 | MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_316 | 316 | MCAN2_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_317 | 317 | MCAN2_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_318 | 318 | MCAN3_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_319 | 319 | MCAN3_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_320 | 320 | MCAN4_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_321 | 321 | MCAN4_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_322 | 322 | MCAN5_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_323 | 323 | MCAN5_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_324 | 324 | MCAN6_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_325 | 325 | MCAN6_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_326 | 326 | MCAN7_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_327 | 327 | MCAN7_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_328 | 328 | MCAN8_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_329 | 329 | MCAN8_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_330 | 330 | MCAN9_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_331 | 331 | MCAN9_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_332 | 332 | MCAN10_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_333 | 333 | MCAN10_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_334 | 334 | MCAN11_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_335 | 335 | MCAN11_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_336 | 336 | MCAN12_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_337 | 337 | MCAN12_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_338 | 338 | MCAN13_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_339 | 339 | MCAN13_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_340 | 340 | MCAN14_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_341 | 341 | MCAN14_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_342 | 342 | MCAN15_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_LVL_IN_343 | 343 | MCAN15_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_LVL_IN_373 | 373 | PCIE1_PCIE_ECC0_CORR_LEVEL_0 |
ESM0_LVL_IN_374 | 374 | PCIE1_PCIE_ECC0_UNCORR_LEVEL_0 |
ESM0_LVL_IN_375 | 375 | PCIE1_PCIE_ECC1_UNCORR_LEVEL_0 |
ESM0_LVL_IN_376 | 376 | PCIE1_PCIE_ASF_NONFATAL_LEVEL_0 |
ESM0_LVL_IN_377 | 377 | PCIE1_PCIE_ASF_FATAL_LEVEL_0 |
ESM0_LVL_IN_378 | 378 | MASTER_SAFETY_GASKET6_TIMED_OUT_0 |
ESM0_LVL_IN_379 | 379 | MASTER_SAFETY_GASKET7_TIMED_OUT_0 |
ESM0_LVL_IN_380 | 380 | MASTER_SAFETY_GASKET2_TIMED_OUT_0 |
ESM0_LVL_IN_381 | 381 | MASTER_SAFETY_GASKET3_TIMED_OUT_0 |
ESM0_LVL_IN_382 | 382 | MASTER_SAFETY_GASKET0_TIMED_OUT_0 |
ESM0_LVL_IN_383 | 383 | MASTER_SAFETY_GASKET1_TIMED_OUT_0 |
ESM0_LVL_IN_384 | 384 | MASTER_SAFETY_GASKET10_TIMED_OUT_0 |
ESM0_LVL_IN_385 | 385 | MASTER_SAFETY_GASKET11_TIMED_OUT_0 |
ESM0_LVL_IN_386 | 386 | MASTER_SAFETY_GASKET12_TIMED_OUT_0 |
ESM0_LVL_IN_387 | 387 | MASTER_SAFETY_GASKET13_TIMED_OUT_0 |
ESM0_LVL_IN_391 | 391 | NAVSS0_VIRTSS_VIRTSS_FFI_PVU0_DST_TIMED_OUT_0 |
ESM0_LVL_IN_392 | 392 | R5FSS0_CORE0_EXP_INTR_0 |
ESM0_LVL_IN_393 | 393 | R5FSS0_CORE1_EXP_INTR_0 |
ESM0_LVL_IN_400 | 400 | TIMEOUT0_TRANS_ERR_LVL_0 |
ESM0_LVL_IN_401 | 401 | TIMEOUT1_TRANS_ERR_LVL_0 |
ESM0_LVL_IN_402 | 402 | TIMEOUT2_TRANS_ERR_LVL_0 |
ESM0_LVL_IN_403 | 403 | TIMEOUT3_TRANS_ERR_LVL_0 |
ESM0_LVL_IN_404 | 404 | TIMEOUT4_TRANS_ERR_LVL_0 |
ESM0_LVL_IN_408 | 408 | NAVSS0_VIRTSS_VIRTSS_FFI_PVU0_CFG_TRANS_ERR_LVL_0 |
ESM0_LVL_IN_409 | 409 | NAVSS0_VIRTSS_VIRTSS_FFI_PVU0_SRC_TRANS_ERR_LVL_0 |
ESM0_LVL_IN_416 | 416 | PDMA9_ECC_SEC_PEND_0 |
ESM0_LVL_IN_417 | 417 | PDMA9_ECC_DED_PEND_0 |
ESM0_LVL_IN_418 | 418 | PDMA10_ECC_SEC_PEND_0 |
ESM0_LVL_IN_419 | 419 | PDMA10_ECC_DED_PEND_0 |
ESM0_LVL_IN_422 | 422 | ECC_AGGR0_CORR_LEVEL_0 |
ESM0_LVL_IN_423 | 423 | ECC_AGGR0_UNCORR_LEVEL_0 |
ESM0_LVL_IN_424 | 424 | ECC_AGGR16_CORR_LEVEL_0 |
ESM0_LVL_IN_425 | 425 | ECC_AGGR16_UNCORR_LEVEL_0 |
ESM0_LVL_IN_426 | 426 | ECC_AGGR17_CORR_LEVEL_0 |
ESM0_LVL_IN_427 | 427 | ECC_AGGR17_UNCORR_LEVEL_0 |
ESM0_LVL_IN_432 | 432 | ECC_AGGR4_CORR_LEVEL_0 |
ESM0_LVL_IN_433 | 433 | ECC_AGGR4_UNCORR_LEVEL_0 |
ESM0_LVL_IN_434 | 434 | ECC_AGGR5_CORR_LEVEL_0 |
ESM0_LVL_IN_435 | 435 | ECC_AGGR5_UNCORR_LEVEL_0 |
ESM0_LVL_IN_436 | 436 | ECC_AGGR6_CORR_LEVEL_0 |
ESM0_LVL_IN_437 | 437 | ECC_AGGR6_UNCORR_LEVEL_0 |
ESM0_LVL_IN_444 | 444 | ECC_AGGR10_CORR_LEVEL_0 |
ESM0_LVL_IN_445 | 445 | ECC_AGGR10_UNCORR_LEVEL_0 |
ESM0_LVL_IN_446 | 446 | ECC_AGGR11_CORR_LEVEL_0 |
ESM0_LVL_IN_447 | 447 | ECC_AGGR11_UNCORR_LEVEL_0 |
ESM0_LVL_IN_456 | 456 | DFTSS0_DFT_SAFETY_123_0 |
ESM0_LVL_IN_457 | 457 | DFTSS0_DFT_SAFETY_MULTI_0 |
ESM0_LVL_IN_458 | 458 | DFTSS0_DFT_SAFETY_ONE_0 |
ESM0_LVL_IN_459 | 459 | PBIST0_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_LVL_IN_460 | 460 | PBIST1_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_LVL_IN_467 | 467 | PBIST2_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_LVL_IN_480 | 480 | PSC0_PSC_MOD_MNLP_MAIN_ALWAYSON_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_481 | 481 | PSC0_PSC_MOD_MNLP_MAIN_TEST_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_482 | 482 | PSC0_PSC_MOD_MNLP_MAIN_PBIST_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_483 | 483 | PSC0_PSC_MOD_MNLP_PER_AUDIO_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_484 | 484 | PSC0_PSC_MOD_MNLP_PER_ATL_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_486 | 486 | PSC0_PSC_MOD_MNLP_PER_MOTOR_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_487 | 487 | PSC0_PSC_MOD_MNLP_PER_MISCIO_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_488 | 488 | PSC0_PSC_MOD_MNLP_PER_GPMC_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_489 | 489 | PSC0_PSC_MOD_MNLP_PER_VPFE_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_491 | 491 | PSC0_PSC_MOD_MNLP_PER_SPARE0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_492 | 492 | PSC0_PSC_MOD_MNLP_PER_SPARE1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_493 | 493 | PSC0_PSC_MOD_MNLP_MAIN_DEBUG_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_494 | 494 | PSC0_PSC_MOD_MNLP_EMIF_DATA_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_495 | 495 | PSC0_PSC_MOD_MNLP_EMIF_CFG_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_498 | 498 | PSC0_PSC_MOD_MNLP_PER_SPARE2_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_499 | 499 | PSC0_PSC_MOD_MNLP_CC_TOP_PBIST_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_500 | 500 | PSC0_PSC_MOD_MNLP_USB_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_503 | 503 | PSC0_PSC_MOD_MNLP_MMC4B_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_505 | 505 | PSC0_PSC_MOD_MNLP_MMC8B_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_509 | 509 | PSC0_PSC_MOD_MNLP_PCIE_1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_513 | 513 | PSC0_PSC_MOD_MNLP_PER_I3C_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_514 | 514 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_515 | 515 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_516 | 516 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_2_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_517 | 517 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_3_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_518 | 518 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_4_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_519 | 519 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_5_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_520 | 520 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_6_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_521 | 521 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_7_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_522 | 522 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_8_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_523 | 523 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_9_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_524 | 524 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_10_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_525 | 525 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_11_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_526 | 526 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_12_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_527 | 527 | PSC0_PSC_MOD_MNLP_MAIN_MCANSS_13_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_528 | 528 | PSC0_PSC_MOD_MNLP_DSS_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_529 | 529 | PSC0_PSC_MOD_MNLP_DSS_PBIST_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_530 | 530 | PSC0_PSC_MOD_MNLP_DSI_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_531 | 531 | PSC0_PSC_MOD_MNLP_EDP_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_532 | 532 | PSC0_PSC_MOD_MNLP_EDP_1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_533 | 533 | PSC0_PSC_MOD_MNLP_CSIRX_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_534 | 534 | PSC0_PSC_MOD_MNLP_CSIRX_1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_535 | 535 | PSC0_PSC_MOD_MNLP_CSIRX_2_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_536 | 536 | PSC0_PSC_MOD_MNLP_CSITX_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_537 | 537 | PSC0_PSC_MOD_MNLP_TX_DPHY_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_538 | 538 | PSC0_PSC_MOD_MNLP_CSIRX_PHY_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_543 | 543 | PSC0_PSC_MOD_MNLP_9GSS_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_544 | 544 | PSC0_PSC_MOD_MNLP_SERDES_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_550 | 550 | PSC0_PSC_MOD_MNLP_DMTIMER_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_551 | 551 | PSC0_PSC_MOD_MNLP_DMTIMER_1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_552 | 552 | PSC0_PSC_MOD_MNLP_DMTIMER_2_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_553 | 553 | PSC0_PSC_MOD_MNLP_DMTIMER_3_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_558 | 558 | PSC0_PSC_MOD_MNLP_A72_CLUSTER_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_559 | 559 | PSC0_PSC_MOD_MNLP_A72_CLUSTER_0_PBIST_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_560 | 560 | PSC0_PSC_MOD_MNLP_A72_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_561 | 561 | PSC0_PSC_MOD_MNLP_A72_1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_573 | 573 | PSC0_PSC_MOD_MNLP_PULSAR_0_R5_0_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_574 | 574 | PSC0_PSC_MOD_MNLP_PULSAR_0_R5_1_CS1_CLKSTOP_REQ_0 |
ESM0_LVL_IN_575 | 575 | PSC0_PSC_MOD_MNLP_PULSAR_PBIST_0_CS1_CLKSTOP_REQ_0 |
ESM0_PLS_IN_608 | 608 | R5FSS0_CORE0_ECC_CORRECTED_PULSE_0 |
ESM0_PLS_IN_609 | 609 | R5FSS0_CORE0_ECC_UNCORRECTED_PULSE_0 |
ESM0_PLS_IN_610 | 610 | R5FSS0_CORE1_ECC_CORRECTED_PULSE_0 |
ESM0_PLS_IN_611 | 611 | R5FSS0_CORE1_ECC_UNCORRECTED_PULSE_0 |
ESM0_PLS_IN_612 | 612 | R5FSS0_COMMON0_SELFTEST_ERR_PULSE_0 |
ESM0_PLS_IN_613 | 613 | R5FSS0_COMMON0_COMPARE_ERR_PULSE_0 |
ESM0_PLS_IN_614 | 614 | R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_0 |
ESM0_PLS_IN_615 | 615 | R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_0 |
ESM0_PLS_IN_616 | 616 | R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0 |
ESM0_PLS_IN_628 | 628 | COMPUTE_CLUSTER0_GIC500SS_AXIM_ERR_0 |
ESM0_PLS_IN_629 | 629 | COMPUTE_CLUSTER0_GIC500SS_ECC_FATAL_0 |
ESM0_PLS_IN_632 | 632 | GPIOMUX_INTRTR0_OUTP_0 |
ESM0_PLS_IN_633 | 633 | GPIOMUX_INTRTR0_OUTP_1 |
ESM0_PLS_IN_634 | 634 | GPIOMUX_INTRTR0_OUTP_2 |
ESM0_PLS_IN_635 | 635 | GPIOMUX_INTRTR0_OUTP_3 |
ESM0_PLS_IN_636 | 636 | GPIOMUX_INTRTR0_OUTP_4 |
ESM0_PLS_IN_637 | 637 | GPIOMUX_INTRTR0_OUTP_5 |
ESM0_PLS_IN_638 | 638 | GPIOMUX_INTRTR0_OUTP_6 |
ESM0_PLS_IN_639 | 639 | GPIOMUX_INTRTR0_OUTP_7 |
ESM0_PLS_IN_656 | 656 | RTI0_INTR_WWD_0 |
ESM0_PLS_IN_657 | 657 | RTI1_INTR_WWD_0 |
ESM0_PLS_IN_664 | 664 | RTI28_INTR_WWD_0 |
ESM0_PLS_IN_665 | 665 | RTI29_INTR_WWD_0 |