SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 9-85 shows the mapping of events to the GIC500 PPI inputs. There are 16 PPI events per A72 core.
PPI events can be configured for either low-level (default) or high-pulse operation.
PPI events represent events 16-31 of each A72 core.
Interrupt Input Line | Interrupt ID | Interrupt Name |
---|---|---|
PPI events for A72SS0_CORE0 | ||
GIC500_PPI0_0_IN_16 | 16 | GLUELOGIC_A72_IPC_INTR_GLUE_IIPC_INTR_Z_8_0 |
GIC500_PPI0_0_IN_22 | 22 | A72SS0_CORE0_COMMIRQ_0 |
GIC500_PPI0_0_IN_23 | 23 | A72SS0_CORE0_PMUIRQ_0 |
GIC500_PPI0_0_IN_24 | 24 | A72SS0_CORE0_CTIIRQ_0 |
GIC500_PPI0_0_IN_25 | 25 | A72SS0_CORE0_VCPUMNTIRQ_0 |
GIC500_PPI0_0_IN_26 | 26 | A72SS0_CORE0_CNTHPIRQ_0 |
GIC500_PPI0_0_IN_27 | 27 | A72SS0_CORE0_CNTVIRQ_0 |
GIC500_PPI0_0_IN_29 | 29 | A72SS0_CORE0_CNTPSIRQ_0 |
GIC500_PPI0_0_IN_30 | 30 | A72SS0_CORE0_CNTPNSIRQ_0 |
PPI events for A72SS0_CORE1 | ||
GIC500_PPI0_1_IN_16 | 16 | GLUELOGIC_A72_IPC_INTR_GLUE_IIPC_INTR_Z_9_0 |
GIC500_PPI0_1_IN_22 | 22 | A72SS0_CORE1_COMMIRQ_0 |
GIC500_PPI0_1_IN_23 | 23 | A72SS0_CORE1_PMUIRQ_0 |
GIC500_PPI0_1_IN_24 | 24 | A72SS0_CORE1_CTIIRQ_0 |
GIC500_PPI0_1_IN_25 | 25 | A72SS0_CORE1_VCPUMNTIRQ_0 |
GIC500_PPI0_1_IN_26 | 26 | A72SS0_CORE1_CNTHPIRQ_0 |
GIC500_PPI0_1_IN_27 | 27 | A72SS0_CORE1_CNTVIRQ_0 |
GIC500_PPI0_1_IN_29 | 29 | A72SS0_CORE1_CNTPSIRQ_0 |
GIC500_PPI0_1_IN_30 | 30 | A72SS0_CORE1_CNTPNSIRQ_0 |