Integrated in the MAIN domain is one instance of high-speed differential interface implemented with Serializer/Deserializer (SERDES) Multi-protocol Multi-link modules with the following main blocks:
- Quad lane PHY with common module for peripheral and Tx clocking handling
- Physical coding sub-block for data translation from/to the parallel interface, as well as data encoding/decoding and ymbol alignment
- MUX module for device interfaces multiplexing into a single SERDES lane (Tx and Rx)
- A wrapper for sending control and reporting status signals from the SerDes and muxes