SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes an ECC aggregator integration in the device, including information about clocks, resets, and hardware requests.
For a list of the device modules and subsystems which have ECC aggregator, see Table 12-5840.
Table 12-5841 shows the integration of an ECC aggregator module.
Table 12-5841 through Table 12-5843 summarize the integration of an ECC aggregator module.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
ECC_AGGR | Same PSC as the corresponding module or subsystem | Same PD as the corresponding module or subsystem | Same LPSC as the corresponding module or subsystem | Same CBASS as the corresponding module or subsystem |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
ECC_AGGR | ECC_CLK | Same as the corresponding module or subsystem(1) | Same as the corresponding module or subsystem(1) | ECC aggregator clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
ECC_AGGR | ECC_RST | Same as the corresponding module or subsystem(1) | Same as the corresponding module or subsystem(1) | ECC aggregator reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
ECC_AGGR | ECC_SEC_INT | See (1) | See (1) | Interrupt for correctable error (SEC) | Level |
ECC_DED_INT | See (1) | See (1) | Interrupt for non-correctable error (DED, parity, redundancy, timeout) | Level | |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
ECC_AGGR | - | - | - | - | - |