SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The POKs are both controlled by and send their output back through the PRG(_PP) module; the PRG(_PP) module.
Each POK is controlled, sampled, and filtered by a specific PRG(_PP) (see POK Modules and Monitored Voltages) and the control register within that PRG(_PP) is where the POKs are controlled (e.g. CTRLMMR_WKUP_PRG_POR_CTRL).
PRG in POR does not support ping-pong.
Mode: | Example Register / Bitfield |
---|---|
Each POK can be configured to apply the undervoltage threshold continuously. 1. OV_SEL is cleared; the threshold voltage is taken from *UV_CTRL 2. POK_PP_EN is cleared | CTRLMMR_WKUP_ POK_VDDR_MCU_UV_CTRL CTRLMMR_WKUP_PRG_PP_MCU_CTRL[9]. POK_VDDR_MCU_OV_SEL = 0 CTRLMMR_WKUP_PRG_PP_MCU_CTRL[19] POK_PP_EN = 0 |
Each POK can be configured to apply the overvoltage threshold continuously. 1. OV_SEL is set; the threshold voltage is taken from *OV_CTRL 2. POK_PP_EN is cleared | CTRLMMR_WKUP_ POK_VDDR_MCU_OV_CTRL CTRLMMR_WKUP_PRG_PP_MCU_CTRL[9]. POK_VDDR_MCU_OV_SEL = 1 CTRLMMR_WKUP_PRG_PP_MCU_CTRL[19] = 0 |
All POK can be configured to apply the undervoltage threshold then the overvoltage threshold iteratively (ping-pong) 1. All OV_SEL are cleared 2. POK_PP_EN is set; the threshold voltage is taken from *UV_CTRL in the UV phase; the threshold voltage is taken from *OV_CTRL in the OV phase | CTRLMMR_WKUP_ POK_VDDR_MCU_UV_CTRL CTRLMMR_WKUP_ POK_VDDR_MCU_OV_CTRL CTRLMMR_WKUP_PRG_PP_MCU_CTRL[10:8] = 000b CTRLMMR_WKUP_PRG_PP_MCU_CTRL[19] = 1 |