SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 12-490 shows a device with integrated EMAC and MDIO interfaced via a RMII connection in a typical system. The individual MCU_CPSW0 and MDIO signals for the RMII interface are summarized in Table 12-926.
The MCU_CPSW0 module integrated in the device supports internal and external clock sources in RMII mode. Figure 12-490 shows the internal clock source for RMII_MHZ_50_CLK clock. It is 50 MHz clock source that is provided on the MCU_CLKOUT0 device pin. This clock has to be routed on the PCB to the MCU_RMII1_REF_CLK device pin and the external PHY, RMII clock input.
For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E).
Figure 12-491 shows the external clock source for RMII_MHZ_50_CLK clock. In this case a 50 MHz clock is available on the PCB and it can be sourced from an oscillator or from the Ethernet PHY. This externally generated clock should be routed to both MCU_RMII1_REF_CLK device pin and the external PHY, RMII clock input.
Signal | Device Pin(s) | I/O(1) | Description |
---|---|---|---|
RMII1_TXD[1:0] | MCU_RMII1_TXD[1:0] | O | Transmit data. The transmit data pins are a collection of 2 bits of data. TXD0 is the least-significant bit (LSB). The signals are synchronized by RMII_MHZ_50_CLK and valid only when RMII1_TX_EN is asserted. |
RMII1_TX_EN | MCU_RMII1_TX_EN | O | RMII transmit enable. The transmit enable signal indicates that the MCU_RMII1_TXD[1:0] pins are generating data for use by the PHY. RMII1_TX_EN is synchronous to RMII_MHZ_50_CLK. |
RMII_MHZ_50_CLK | MCU_RMII1_REF_CLK | I | RMII 50MHz reference clock. |
The reference clock is used to synchronize all RMII signals. RMII_MHZ_50_CLK must be continuous and fixed at 50 MHz. | |||
RMII1_RXD[1:0] | MCU_RMII1_RXD[1:0] | I | Receive data. The receive data pins are a collection of 2 bits of data. RXD0 is the least-significant bit (LSB). The signals are synchronized by RMII_MHZ_50_CLK and valid only when RMII1_CRS_DV is asserted and RMII1_RX_ER is de-asserted. |
RMII1_CRS_DV | MCU_RMII1_CRS_DV | I | Carrier sense/receive data valid. Multiplexed signal between carrier sense and receive data valid. |
RMII1_RX_ER | MCU_RMII1_RX_ER | I | Receive error. The receive error signal is asserted to indicate that an error was detected in the received frame. |
MDIO_MCLK | MCU_MDIO0_MDC | O | Management data clock (MDIO_MCLK). The MDIO data clock is sourced by the MDIO module on the system. It is used to synchronize MDIO data access operations done on the MCU_MDIO0_MDIO pin. |
MDIO_MDIO | MCU_MDIO0_MDIO | I/O | MDIO data pin drives PHY management data into and out of the PHY by way of an access frame consisting of start of frame, read/write indication, PHY address, register address, and data bit cycles. The MCU_MDIO0_MDIO pin acts as an output for all but the data bit cycles at which time it is an input for read operations. |