SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Table 12-5436 lists the memory-mapped registers for the RTI. All register offset addresses not listed in Table 12-5436 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
RTI0_CFG | 0220 0000h |
RTI1_CFG | 0221 0000h |
RTI28_CFG | 023C 0000h |
RTI29_CFG | 023D 0000h |
MCU_RTI0_CFG | 4060 0000h |
MCU_RTI1_CFG | 4061 0000h |
Offset | Acronym | Register Name | RTI0_CFG Physical Address | RTI1_CFG Physical Address |
---|---|---|---|---|
0h | RTI_GCTRL | RTI Global Control Register | 0220 0000h | 0221 0000h |
4h | RTI_TBCTRL | RTI Timebase Control Register | 0220 0004h | 0221 0004h |
8h | RTI_CAPCTRL | RTI Capture Control Register | 0220 0008h | 0221 0008h |
Ch | RTI_COMPCTRL | RTI Compare Control Register | 0220 000Ch | 0221 000Ch |
10h | RTI_FRC0 | RTI Free Running Counter 0 Register | 0220 0010h | 0221 0010h |
14h | RTI_UC0 | RTI Up Counter 0 Register | 0220 0014h | 0221 0014h |
18h | RTI_CPUC0 | RTI Compare Up Counter 0 Register | 0220 0018h | 0221 0018h |
20h | RTI_CAFRC0 | RTI Capture Free Running Counter 0 Register | 0220 0020h | 0221 0020h |
24h | RTI_CAUC0 | RTI Capture Up Counter 0 Register | 0220 0024h | 0221 0024h |
30h | RTI_FRC1 | RTI Free Running Counter 1 Register | 0220 0030h | 0221 0030h |
34h | RTI_UC1 | RTI Up Counter 1 Register | 0220 0034h | 0221 0034h |
38h | RTI_CPUC1 | RTI Compare Up Counter 1 Register | 0220 0038h | 0221 0038h |
40h | RTI_CAFRC1 | RTI Capture Free Running Counter 1 Register | 0220 0040h | 0221 0040h |
44h | RTI_CAUC1 | RTI Capture Up Counter 1 Register | 0220 0044h | 0221 0044h |
50h | RTI_COMP0 | RTI Compare 0 Register | 0220 0050h | 0221 0050h |
54h | RTI_UDCP0 | RTI Update Compare 0 Register | 0220 0054h | 0221 0054h |
58h | RTI_COMP1 | RTI Compare 1 Register | 0220 0058h | 0221 0058h |
5Ch | RTI_UDCP1 | RTI Update Compare 1 Register | 0220 005Ch | 0221 005Ch |
60h | RTI_COMP2 | RTI Compare 2 Register | 0220 0060h | 0221 0060h |
64h | RTI_UDCP2 | RTI Update Compare 2 Register | 0220 0064h | 0221 0064h |
68h | RTI_COMP3 | RTI Compare 3 Register | 0220 0068h | 0221 0068h |
6Ch | RTI_UDCP3 | RTI Update Compare 3 Register | 0220 006Ch | 0221 006Ch |
70h | RTI_TBLCOMP | RTI External Clock Timebase Low Compare Register | 0220 0070h | 0221 0070h |
74h | RTI_TBHCOMP | RTI External Clock Timebase High Compare Register | 0220 0074h | 0221 0074h |
80h | RTI_SETINT | RTI Set/Status Interrupt Register | 0220 0080h | 0221 0080h |
84h | RTI_CLEARINT | RTI Clear/Status Interrupt Register | 0220 0084h | 0221 0084h |
88h | RTI_INTFLAG | RTI Interrupt Flag Register | 0220 0088h | 0221 0088h |
90h | RTI_DWDCTRL | Digital Watchdog Control Register | 0220 0090h | 0221 0090h |
94h | RTI_DWDPRLD | Digital Watchdog Preload Register | 0220 0094h | 0221 0094h |
98h | RTI_WDSTATUS | Watchdog Status Register | 0220 0098h | 0221 0098h |
9Ch | RTI_WDKEY | Watchdog Key Register | 0220 009Ch | 0221 009Ch |
A0h | RTI_DWDCNTR | Digital Watchdog Down Counter | 0220 00A0h | 0221 00A0h |
A4h | RTI_WWDRXNCTRL | Digital Windowed Watchdog Reaction Control | 0220 00A4h | 0221 00A4h |
A8h | RTI_WWDSIZECTRL | Digital Windowed Watchdog Window Size Control | 0220 00A8h | 0221 00A8h |
ACh | RTI_INTCLRENABLE | RTI Compare Interrupt Clear Enable Register | 0220 00ACh | 0221 00ACh |
B0h | RTI_COMP0CLR | RTI Compare 0 Clear Register | 0220 00B0h | 0221 00B0h |
B4h | RTI_COMP1CLR | RTI Compare 1 Clear Register | 0220 00B4h | 0221 00B4h |
B8h | RTI_COMP2CLR | RTI Compare 2 Clear Register | 0220 00B8h | 0221 00B8h |
BCh | RTI_COMP3CLR | RTI Compare 3 Clear Register | 0220 00BCh | 0221 00BCh |
Offset | Acronym | Register Name | RTI28_CFG Physical Address | RTI29_CFG Physical Address |
---|---|---|---|---|
0h | RTI_GCTRL | RTI Global Control Register | 023C 0000h | 023D 0000h |
4h | RTI_TBCTRL | RTI Timebase Control Register | 023C 0004h | 023D 0004h |
8h | RTI_CAPCTRL | RTI Capture Control Register | 023C 0008h | 023D 0008h |
Ch | RTI_COMPCTRL | RTI Compare Control Register | 023C 000Ch | 023D 000Ch |
10h | RTI_FRC0 | RTI Free Running Counter 0 Register | 023C 0010h | 023D 0010h |
14h | RTI_UC0 | RTI Up Counter 0 Register | 023C 0014h | 023D 0014h |
18h | RTI_CPUC0 | RTI Compare Up Counter 0 Register | 023C 0018h | 023D 0018h |
20h | RTI_CAFRC0 | RTI Capture Free Running Counter 0 Register | 023C 0020h | 023D 0020h |
24h | RTI_CAUC0 | RTI Capture Up Counter 0 Register | 023C 0024h | 023D 0024h |
30h | RTI_FRC1 | RTI Free Running Counter 1 Register | 023C 0030h | 023D 0030h |
34h | RTI_UC1 | RTI Up Counter 1 Register | 023C 0034h | 023D 0034h |
38h | RTI_CPUC1 | RTI Compare Up Counter 1 Register | 023C 0038h | 023D 0038h |
40h | RTI_CAFRC1 | RTI Capture Free Running Counter 1 Register | 023C 0040h | 023D 0040h |
44h | RTI_CAUC1 | RTI Capture Up Counter 1 Register | 023C 0044h | 023D 0044h |
50h | RTI_COMP0 | RTI Compare 0 Register | 023C 0050h | 023D 0050h |
54h | RTI_UDCP0 | RTI Update Compare 0 Register | 023C 0054h | 023D 0054h |
58h | RTI_COMP1 | RTI Compare 1 Register | 023C 0058h | 023D 0058h |
5Ch | RTI_UDCP1 | RTI Update Compare 1 Register | 023C 005Ch | 023D 005Ch |
60h | RTI_COMP2 | RTI Compare 2 Register | 023C 0060h | 023D 0060h |
64h | RTI_UDCP2 | RTI Update Compare 2 Register | 023C 0064h | 023D 0064h |
68h | RTI_COMP3 | RTI Compare 3 Register | 023C 0068h | 023D 0068h |
6Ch | RTI_UDCP3 | RTI Update Compare 3 Register | 023C 006Ch | 023D 006Ch |
70h | RTI_TBLCOMP | RTI External Clock Timebase Low Compare Register | 023C 0070h | 023D 0070h |
74h | RTI_TBHCOMP | RTI External Clock Timebase High Compare Register | 023C 0074h | 023D 0074h |
80h | RTI_SETINT | RTI Set/Status Interrupt Register | 023C 0080h | 023D 0080h |
84h | RTI_CLEARINT | RTI Clear/Status Interrupt Register | 023C 0084h | 023D 0084h |
88h | RTI_INTFLAG | RTI Interrupt Flag Register | 023C 0088h | 023D 0088h |
90h | RTI_DWDCTRL | Digital Watchdog Control Register | 023C 0090h | 023D 0090h |
94h | RTI_DWDPRLD | Digital Watchdog Preload Register | 023C 0094h | 023D 0094h |
98h | RTI_WDSTATUS | Watchdog Status Register | 023C 0098h | 023D 0098h |
9Ch | RTI_WDKEY | Watchdog Key Register | 023C 009Ch | 023D 009Ch |
A0h | RTI_DWDCNTR | Digital Watchdog Down Counter | 023C 00A0h | 023D 00A0h |
A4h | RTI_WWDRXNCTRL | Digital Windowed Watchdog Reaction Control | 023C 00A4h | 023D 00A4h |
A8h | RTI_WWDSIZECTRL | Digital Windowed Watchdog Window Size Control | 023C 00A8h | 023D 00A8h |
ACh | RTI_INTCLRENABLE | RTI Compare Interrupt Clear Enable Register | 023C 00ACh | 023D 00ACh |
B0h | RTI_COMP0CLR | RTI Compare 0 Clear Register | 023C 00B0h | 023D 00B0h |
B4h | RTI_COMP1CLR | RTI Compare 1 Clear Register | 023C 00B4h | 023D 00B4h |
B8h | RTI_COMP2CLR | RTI Compare 2 Clear Register | 023C 00B8h | 023D 00B8h |
BCh | RTI_COMP3CLR | RTI Compare 3 Clear Register | 023C 00BCh | 023D 00BCh |
Offset | Acronym | Register Name | MCU_RTI0_CFG Physical Address | MCU_RTI1_CFG Physical Address |
---|---|---|---|---|
0h | RTI_GCTRL | RTI Global Control Register | 4060 0000h | 4061 0000h |
4h | RTI_TBCTRL | RTI Timebase Control Register | 4060 0004h | 4061 0004h |
8h | RTI_CAPCTRL | RTI Capture Control Register | 4060 0008h | 4061 0008h |
Ch | RTI_COMPCTRL | RTI Compare Control Register | 4060 000Ch | 4061 000Ch |
10h | RTI_FRC0 | RTI Free Running Counter 0 Register | 4060 0010h | 4061 0010h |
14h | RTI_UC0 | RTI Up Counter 0 Register | 4060 0014h | 4061 0014h |
18h | RTI_CPUC0 | RTI Compare Up Counter 0 Register | 4060 0018h | 4061 0018h |
20h | RTI_CAFRC0 | RTI Capture Free Running Counter 0 Register | 4060 0020h | 4061 0020h |
24h | RTI_CAUC0 | RTI Capture Up Counter 0 Register | 4060 0024h | 4061 0024h |
30h | RTI_FRC1 | RTI Free Running Counter 1 Register | 4060 0030h | 4061 0030h |
34h | RTI_UC1 | RTI Up Counter 1 Register | 4060 0034h | 4061 0034h |
38h | RTI_CPUC1 | RTI Compare Up Counter 1 Register | 4060 0038h | 4061 0038h |
40h | RTI_CAFRC1 | RTI Capture Free Running Counter 1 Register | 4060 0040h | 4061 0040h |
44h | RTI_CAUC1 | RTI Capture Up Counter 1 Register | 4060 0044h | 4061 0044h |
50h | RTI_COMP0 | RTI Compare 0 Register | 4060 0050h | 4061 0050h |
54h | RTI_UDCP0 | RTI Update Compare 0 Register | 4060 0054h | 4061 0054h |
58h | RTI_COMP1 | RTI Compare 1 Register | 4060 0058h | 4061 0058h |
5Ch | RTI_UDCP1 | RTI Update Compare 1 Register | 4060 005Ch | 4061 005Ch |
60h | RTI_COMP2 | RTI Compare 2 Register | 4060 0060h | 4061 0060h |
64h | RTI_UDCP2 | RTI Update Compare 2 Register | 4060 0064h | 4061 0064h |
68h | RTI_COMP3 | RTI Compare 3 Register | 4060 0068h | 4061 0068h |
6Ch | RTI_UDCP3 | RTI Update Compare 3 Register | 4060 006Ch | 4061 006Ch |
70h | RTI_TBLCOMP | RTI External Clock Timebase Low Compare Register | 4060 0070h | 4061 0070h |
74h | RTI_TBHCOMP | RTI External Clock Timebase High Compare Register | 4060 0074h | 4061 0074h |
80h | RTI_SETINT | RTI Set/Status Interrupt Register | 4060 0080h | 4061 0080h |
84h | RTI_CLEARINT | RTI Clear/Status Interrupt Register | 4060 0084h | 4061 0084h |
88h | RTI_INTFLAG | RTI Interrupt Flag Register | 4060 0088h | 4061 0088h |
90h | RTI_DWDCTRL | Digital Watchdog Control Register | 4060 0090h | 4061 0090h |
94h | RTI_DWDPRLD | Digital Watchdog Preload Register | 4060 0094h | 4061 0094h |
98h | RTI_WDSTATUS | Watchdog Status Register | 4060 0098h | 4061 0098h |
9Ch | RTI_WDKEY | Watchdog Key Register | 4060 009Ch | 4061 009Ch |
A0h | RTI_DWDCNTR | Digital Watchdog Down Counter | 4060 00A0h | 4061 00A0h |
A4h | RTI_WWDRXNCTRL | Digital Windowed Watchdog Reaction Control | 4060 00A4h | 4061 00A4h |
A8h | RTI_WWDSIZECTRL | Digital Windowed Watchdog Window Size Control | 4060 00A8h | 4061 00A8h |
ACh | RTI_INTCLRENABLE | RTI Compare Interrupt Clear Enable Register | 4060 00ACh | 4061 00ACh |
B0h | RTI_COMP0CLR | RTI Compare 0 Clear Register | 4060 00B0h | 4061 00B0h |
B4h | RTI_COMP1CLR | RTI Compare 1 Clear Register | 4060 00B4h | 4061 00B4h |
B8h | RTI_COMP2CLR | RTI Compare 2 Clear Register | 4060 00B8h | 4061 00B8h |
BCh | RTI_COMP3CLR | RTI Compare 3 Clear Register | 4060 00BCh | 4061 00BCh |
RTI_GCTRL is shown in Figure 12-2847 and described in Table 12-5440.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0000h |
RTI1_CFG | 0221 0000h |
RTI28_CFG | 023C 0000h |
RTI29_CFG | 023D 0000h |
MCU_RTI0_CFG | 4060 0000h |
MCU_RTI1_CFG | 4061 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
COS | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNT1EN | CNT0EN | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | RESERVED | R | 0h | Reserved |
15 | COS | R/W | 0h | Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. |
14-2 | RESERVED | R | 0h | Reserved. |
1 | CNT1EN | R/W | 0h | Counter 1 Enable. |
0 | CNT0EN | R/W | 0h | Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). |
RTI_TBCTRL is shown in Figure 12-2848 and described in Table 12-5442.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0004h |
RTI1_CFG | 0221 0004h |
RTI28_CFG | 023C 0004h |
RTI29_CFG | 023D 0004h |
MCU_RTI0_CFG | 4060 0004h |
MCU_RTI1_CFG | 4061 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INC | TBEXT | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | INC | R/W | 0h | This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. |
0 | TBEXT | R/W | 0h | The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. |
RTI_CAPCTRL is shown in Figure 12-2849 and described in Table 12-5444.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0008h |
RTI1_CFG | 0221 0008h |
RTI28_CFG | 023C 0008h |
RTI29_CFG | 023D 0008h |
MCU_RTI0_CFG | 4060 0008h |
MCU_RTI1_CFG | 4061 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CAPCNTR1 | CAPCNTR0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CAPCNTR1 | R/W | 0h | Capture Counter 1. |
0 | CAPCNTR0 | R/W | 0h | Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. |
RTI_COMPCTRL is shown in Figure 12-2850 and described in Table 12-5446.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 000Ch |
RTI1_CFG | 0221 000Ch |
RTI28_CFG | 023C 000Ch |
RTI29_CFG | 023D 000Ch |
MCU_RTI0_CFG | 4060 000Ch |
MCU_RTI1_CFG | 4061 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COMPSEL3 | RESERVED | COMPSEL2 | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMPSEL1 | RESERVED | COMPSEL0 | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12 | COMPSEL3 | R/W | 0h | Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. |
11-9 | RESERVED | R | 0h | Reserved |
8 | COMPSEL2 | R/W | 0h | Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. |
7-5 | RESERVED | R | 0h | Reserved |
4 | COMPSEL1 | R/W | 0h | Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. |
3-1 | RESERVED | R | 0h | Reserved |
0 | COMPSEL0 | R/W | 0h | Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. |
RTI_FRC0 is shown in Figure 12-2851 and described in Table 12-5448.
Return to Summary Table.
This registers holds the current value of the Free Running Counter 0 and will be updated continuously.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0010h |
RTI1_CFG | 0221 0010h |
RTI28_CFG | 023C 0010h |
RTI29_CFG | 023D 0010h |
MCU_RTI0_CFG | 4060 0010h |
MCU_RTI1_CFG | 4061 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRC0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FRC0 | R/W | 0h | Free Running Counter 0. This registers holds the
current value of the Free Running Counter 0 and will be updated
continuously. |
RTI_UC0 is shown in Figure 12-2852 and described in Table 12-5450.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0014h |
RTI1_CFG | 0221 0014h |
RTI28_CFG | 023C 0014h |
RTI29_CFG | 023D 0014h |
MCU_RTI0_CFG | 4060 0014h |
MCU_RTI1_CFG | 4061 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UC0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UC0 | R/W | 0h | Up Counter 0. This registers holds the current
value of the Up Counter 0 and prescales the RTI clock. It will
be only updated by a previous read of Free Running Counter 0.
This gives effectively a 64 bit read of both counters, without
having the problem of a counter being updated between two
consecutive reads on Up Counter 0 and Free Running Counter 0. |
RTI_CPUC0 is shown in Figure 12-2853 and described in Table 12-5452.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0018h |
RTI1_CFG | 0221 0018h |
RTI28_CFG | 023C 0018h |
RTI29_CFG | 023D 0018h |
MCU_RTI0_CFG | 4060 0018h |
MCU_RTI1_CFG | 4061 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPUC0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CPUC0 | R/W | 0h | Compare Up Counter 0. This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI. |
RTI_CAFRC0 is shown in Figure 12-2854 and described in Table 12-5454.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0020h |
RTI1_CFG | 0221 0020h |
RTI28_CFG | 023C 0020h |
RTI29_CFG | 023D 0020h |
MCU_RTI0_CFG | 4060 0020h |
MCU_RTI1_CFG | 4061 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAFRC0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAFRC0 | R | 0h | Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs, controlled by the external capture control block. |
RTI_CAUC0 is shown in Figure 12-2855 and described in Table 12-5456.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0024h |
RTI1_CFG | 0221 0024h |
RTI28_CFG | 023C 0024h |
RTI29_CFG | 023D 0024h |
MCU_RTI0_CFG | 4060 0024h |
MCU_RTI1_CFG | 4061 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAUC0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAUC0 | R | 0h | Capture Up Counter 0. This registers captures the
current value of the Up Counter 0 when an event occurs,
controlled by the external capture control block. The read
sequence has to be the same as with Up Counter 0 and Free
Running Counter 0. So the RTI_CAFRC0 register has to be read
first, before the RTI_CAUC0 register is read. This sequence
ensures that the value of the RTI_CAUC0 register is the
corresponding value to the RTI_CAFRC0 register, even if another
capture event happens in between the two reads. |
RTI_FRC1 is shown in Figure 12-2856 and described in Table 12-5458.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0030h |
RTI1_CFG | 0221 0030h |
RTI28_CFG | 023C 0030h |
RTI29_CFG | 023D 0030h |
MCU_RTI0_CFG | 4060 0030h |
MCU_RTI1_CFG | 4061 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRC1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FRC1 | R/W | 0h | Free Running Counter 1. This registers holds the
current value of the Free Running Counter 1 and will be updated
continuously. |
RTI_UC1 is shown in Figure 12-2857 and described in Table 12-5460.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0034h |
RTI1_CFG | 0221 0034h |
RTI28_CFG | 023C 0034h |
RTI29_CFG | 023D 0034h |
MCU_RTI0_CFG | 4060 0034h |
MCU_RTI1_CFG | 4061 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UC1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UC1 | R/W | 0h | Up Counter 1. This registers holds the current
value of the Up Counter 1 and prescales the RTI clock. It will
be only updated by a previous read of Free Running Counter 1.
This gives effectively a 64 bit read of both counters, without
having the problem of a counter being updated between two
consecutive reads on Up Counter 1 and Free Running Counter 1. |
RTI_CPUC1 is shown in Figure 12-2858 and described in Table 12-5462.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0038h |
RTI1_CFG | 0221 0038h |
RTI28_CFG | 023C 0038h |
RTI29_CFG | 023D 0038h |
MCU_RTI0_CFG | 4060 0038h |
MCU_RTI1_CFG | 4061 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPUC1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CPUC1 | R/W | 0h | Compare Up Counter 1. This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI. |
RTI_CAFRC1 is shown in Figure 12-2859 and described in Table 12-5464.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0040h |
RTI1_CFG | 0221 0040h |
RTI28_CFG | 023C 0040h |
RTI29_CFG | 023D 0040h |
MCU_RTI0_CFG | 4060 0040h |
MCU_RTI1_CFG | 4061 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAFRC1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAFRC1 | R | 0h | Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs, controlled by the external capture control block. |
RTI_CAUC1 is shown in Figure 12-2860 and described in Table 12-5466.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0044h |
RTI1_CFG | 0221 0044h |
RTI28_CFG | 023C 0044h |
RTI29_CFG | 023D 0044h |
MCU_RTI0_CFG | 4060 0044h |
MCU_RTI1_CFG | 4061 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAUC1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAUC1 | R | 0h | Capture Up Counter 1. This registers captures the
current value of the Up Counter 1 when an event occurs,
controlled by the external capture control block. The read
sequence has to be the same as with Up Counter 1 and Free
Running Counter 1. So the RTI_CAFRC1 register has to be read
first, before the RTI_CAUC1 register is read. This sequence
ensures that the value of the RTI_CAUC0 register is the
corresponding value to the RTI_CAFRC0 register, even if another
capture event happens in between the two reads. |
RTI_COMP0 is shown in Figure 12-2861 and described in Table 12-5468.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0050h |
RTI1_CFG | 0221 0050h |
RTI28_CFG | 023C 0050h |
RTI29_CFG | 023D 0050h |
MCU_RTI0_CFG | 4060 0050h |
MCU_RTI1_CFG | 4061 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP0 | R/W | 0h | Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP0 is shown in Figure 12-2862 and described in Table 12-5470.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0054h |
RTI1_CFG | 0221 0054h |
RTI28_CFG | 023C 0054h |
RTI29_CFG | 023D 0054h |
MCU_RTI0_CFG | 4060 0054h |
MCU_RTI1_CFG | 4061 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP0 | R/W | 0h | Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_COMP1 is shown in Figure 12-2863 and described in Table 12-5472.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0058h |
RTI1_CFG | 0221 0058h |
RTI28_CFG | 023C 0058h |
RTI29_CFG | 023D 0058h |
MCU_RTI0_CFG | 4060 0058h |
MCU_RTI1_CFG | 4061 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP1 | R/W | 0h | Compare 1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP1 is shown in Figure 12-2864 and described in Table 12-5474.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 005Ch |
RTI1_CFG | 0221 005Ch |
RTI28_CFG | 023C 005Ch |
RTI29_CFG | 023D 005Ch |
MCU_RTI0_CFG | 4060 005Ch |
MCU_RTI1_CFG | 4061 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP1 | R/W | 0h | Update Compare 1 Register. This registers holds a value, which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_COMP2 is shown in Figure 12-2865 and described in Table 12-5476.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0060h |
RTI1_CFG | 0221 0060h |
RTI28_CFG | 023C 0060h |
RTI29_CFG | 023D 0060h |
MCU_RTI0_CFG | 4060 0060h |
MCU_RTI1_CFG | 4061 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP2 | R/W | 0h | Compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP2 is shown in Figure 12-2866 and described in Table 12-5478.
Return to Summary Table.
This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0064h |
RTI1_CFG | 0221 0064h |
RTI28_CFG | 023C 0064h |
RTI29_CFG | 023D 0064h |
MCU_RTI0_CFG | 4060 0064h |
MCU_RTI1_CFG | 4061 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP2 | R/W | 0h | Update Compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_COMP3 is shown in Figure 12-2867 and described in Table 12-5480.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0068h |
RTI1_CFG | 0221 0068h |
RTI28_CFG | 023C 0068h |
RTI29_CFG | 023D 0068h |
MCU_RTI0_CFG | 4060 0068h |
MCU_RTI1_CFG | 4061 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP3 | R/W | 0h | Compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. |
RTI_UDCP3 is shown in Figure 12-2868 and described in Table 12-5482.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 006Ch |
RTI1_CFG | 0221 006Ch |
RTI28_CFG | 023C 006Ch |
RTI29_CFG | 023D 006Ch |
MCU_RTI0_CFG | 4060 006Ch |
MCU_RTI1_CFG | 4061 006Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDCP3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UDCP3 | R/W | 0h | Update Compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. |
RTI_TBLCOMP is shown in Figure 12-2869 and described in Table 12-5484.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0070h |
RTI1_CFG | 0221 0070h |
RTI28_CFG | 023C 0070h |
RTI29_CFG | 023D 0070h |
MCU_RTI0_CFG | 4060 0070h |
MCU_RTI1_CFG | 4061 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBLCOMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TBLCOMP | R | 0h | Reserved |
RTI_TBHCOMP is shown in Figure 12-2870 and described in Table 12-5486.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0074h |
RTI1_CFG | 0221 0074h |
RTI28_CFG | 023C 0074h |
RTI29_CFG | 023D 0074h |
MCU_RTI0_CFG | 4060 0074h |
MCU_RTI1_CFG | 4061 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBHCOMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TBHCOMP | R | 0h | Reserved |
RTI_SETINT is shown in Figure 12-2871 and described in Table 12-5488.
Return to Summary Table.
This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0080h |
RTI1_CFG | 0221 0080h |
RTI28_CFG | 023C 0080h |
RTI29_CFG | 023D 0080h |
MCU_RTI0_CFG | 4060 0080h |
MCU_RTI1_CFG | 4061 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SETOVL1INT | SETOVL0INT | SETTBINT | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SETDMA3 | SETDMA2 | SETDMA1 | SETDMA0 | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SETINT3 | SETINT2 | SETINT1 | SETINT0 | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18 | SETOVL1INT | R/W1S | 0h | Set Free Running Counter 1 Overflow Interrupt. |
17 | SETOVL0INT | R/W1S | 0h | Set Free Running Counter 0 Overflow Interrupt. |
16 | SETTBINT | R/W1S | 0h |
User and privilege mode (read): |
15-12 | RESERVED | R | 0h | Reserved |
11 | SETDMA3 | R/W1S | 0h | Set Compare DMA Request 3. |
10 | SETDMA2 | R/W1S | 0h | Set Compare DMA Request 2. |
9 | SETDMA1 | R/W1S | 0h | Set Compare DMA Request 1. |
8 | SETDMA0 | R/W1S | 0h | Set Compare DMA Request 0. |
7-4 | RESERVED | R | 0h | Reserved |
3 | SETINT3 | R/W1S | 0h | Set Compare Interrupt 3. |
2 | SETINT2 | R/W1S | 0h | Set Compare Interrupt 2. |
1 | SETINT1 | R/W1S | 0h | Set Compare Interrupt 1. |
0 | SETINT0 | R/W1S | 0h | Set Compare Interrupt 0. |
RTI_CLEARINT is shown in Figure 12-2872 and described in Table 12-5490.
Return to Summary Table.
This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0084h |
RTI1_CFG | 0221 0084h |
RTI28_CFG | 023C 0084h |
RTI29_CFG | 023D 0084h |
MCU_RTI0_CFG | 4060 0084h |
MCU_RTI1_CFG | 4061 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CLEAROVL1INT | CLEAROVL0INT | CLEARTBINT | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLEARDMA3 | CLEARDMA2 | CLEARDMA1 | CLEARDMA0 | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLEARINT3 | CLEARINT2 | CLEARINT1 | CLEARINT0 | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18 | CLEAROVL1INT | R/W1C | 0h | Clear Free Running Counter 1 Overflow Interrupt. |
17 | CLEAROVL0INT | R/W1C | 0h | Clear Free Running Counter 0 Overflow Interrupt. |
16 | CLEARTBINT | R/W1C | 0h |
|
15-12 | RESERVED | R | 0h | Reserved |
11 | CLEARDMA3 | R/W1C | 0h | Clear Compare DMA Request 3. |
10 | CLEARDMA2 | R/W1C | 0h | Clear Compare DMA Request 2. |
9 | CLEARDMA1 | R/W1C | 0h | Clear Compare DMA Request 1. |
8 | CLEARDMA0 | R/W1C | 0h | Clear Compare DMA Request 0. |
7-4 | RESERVED | R | 0h | Reserved |
3 | CLEARINT3 | R/W1C | 0h | Clear Compare Interrupt 3. |
2 | CLEARINT2 | R/W1C | 0h | Clear Compare Interrupt 2. |
1 | CLEARINT1 | R/W1C | 0h | Clear Compare Interrupt 1. |
0 | CLEARINT0 | R/W1C | 0h | Clear Compare Interrupt 0. |
RTI_INTFLAG is shown in Figure 12-2873 and described in Table 12-5492.
Return to Summary Table.
The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0088h |
RTI1_CFG | 0221 0088h |
RTI28_CFG | 023C 0088h |
RTI29_CFG | 023D 0088h |
MCU_RTI0_CFG | 4060 0088h |
MCU_RTI1_CFG | 4061 0088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OVL1INT | OVL0INT | TBINT | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT3 | INT2 | INT1 | INT0 | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18 | OVL1INT | R/W1C | 0h | Free Running Counter 1 Overflow Interrupt Flag. |
17 | OVL0INT | R/W1C | 0h | Free Running Counter 0 Overflow Interrupt Flag. |
16 | TBINT | R/W1C | 0h | User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. |
15-4 | RESERVED | R | 0h | Reserved |
3 | INT3 | R/W1C | 0h | Interrupt Flag 3. |
2 | INT2 | R/W1C | 0h | Interrupt Flag 2. |
1 | INT1 | R/W1C | 0h | Interrupt Flag 1. |
0 | INT0 | R/W1C | 0h | Interrupt Flag 0. |
RTI_DWDCTRL is shown in Figure 12-2874 and described in Table 12-5494.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The RTI_DWDCTRL register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0090h |
RTI1_CFG | 0221 0090h |
RTI28_CFG | 023C 0090h |
RTI29_CFG | 023D 0090h |
MCU_RTI0_CFG | 4060 0090h |
MCU_RTI1_CFG | 4061 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DWDCTRL | |||||||||||||||||||||||||||||||
R/W-5312ACEDh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DWDCTRL | R/W | 5312ACEDh | Digital Watchdog Control. |
RTI_DWDPRLD is shown in Figure 12-2875 and described in Table 12-5496.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0094h |
RTI1_CFG | 0221 0094h |
RTI28_CFG | 023C 0094h |
RTI29_CFG | 023D 0094h |
MCU_RTI0_CFG | 4060 0094h |
MCU_RTI1_CFG | 4061 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DWDPRLD | ||||||||||||||||||||||||||||||
R-0h | R/W-FFFh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-0 | DWDPRLD | R/W | FFFh | Digital Watchdog Preload Value. |
RTI_WDSTATUS is shown in Figure 12-2876 and described in Table 12-5498.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 0098h |
RTI1_CFG | 0221 0098h |
RTI28_CFG | 023C 0098h |
RTI29_CFG | 023D 0098h |
MCU_RTI0_CFG | 4060 0098h |
MCU_RTI1_CFG | 4061 0098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DWWD_ST | END | START | KEYST | DWDST | AWDST | |
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | DWWD_ST | R/W1C | 0h | Windowed Watchdog Status. This bit denotes whether
the time-window defined by the windowed watchdog configuration
has been violated, or if a wrong key or key sequence was written
to service the watchdog. |
4 | END | R/W1C | 0h | Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. |
3 | START | R/W1C | 0h | Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. |
2 | KEYST | R/W1C | 0h | Watchdog KeyStatus. This bit denotes a reset
generated by a wrong key or a wrong key-sequence written to the
RTI_WDKEY register. |
1 | DWDST | R/W1C | 0h | Digital Watchdog Status. Status flag and is maintained for compatibility reasons. |
0 | AWDST | R/W1C | 0h | Analog Watchdog Status. |
RTI_WDKEY is shown in Figure 12-2877 and described in Table 12-5500.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 009Ch |
RTI1_CFG | 0221 009Ch |
RTI28_CFG | 023C 009Ch |
RTI29_CFG | 023D 009Ch |
MCU_RTI0_CFG | 4060 009Ch |
MCU_RTI1_CFG | 4061 009Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDKEY | ||||||||||||||||||||||||||||||
R-0h | R/W-A35Ch | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description | ||
---|---|---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved | ||
15-0 | WDKEY | R/W | A35Ch | Watchdog Key. Example of a WDKEY sequence Step -> Value written to WDKEY -> Result 1 -> 0x0A35C -> No Action 2 -> 0x0A35C -> No Action 3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 4 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 5 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 6 -> 0x0A35C -> Watchdog is reset 7 -> 0x0A35C -> No Action 8 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 9 -> 0x0A35C -> Watchdog is reset 10 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C 11 -> 0x02345 -> System reset; incorrect value written to WDKEY |
RTI_DWDCNTR is shown in Figure 12-2878 and described in Table 12-5502.
Return to Summary Table.
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00A0h |
RTI1_CFG | 0221 00A0h |
RTI28_CFG | 023C 00A0h |
RTI29_CFG | 023D 00A0h |
MCU_RTI0_CFG | 4060 00A0h |
MCU_RTI1_CFG | 4061 00A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DWDCNTR | ||||||||||||||
R-0h | R-01FFFFFFh | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DWDCNTR | |||||||||||||||
R-01FFFFFFh | |||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24-0 | DWDCNTR | R | 01FFFFFFh | Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz, a watchdog reset will be generated in 1 second. |
RTI_WWDRXNCTRL is shown in Figure 12-2879 and described in Table 12-5504.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00A4h |
RTI1_CFG | 0221 00A4h |
RTI28_CFG | 023C 00A4h |
RTI29_CFG | 023D 00A4h |
MCU_RTI0_CFG | 4060 00A4h |
MCU_RTI1_CFG | 4061 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WWDRXN | ||||||||||||||
R-0h | R/W-5h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | WWDRXN | R/W | 5h | Digital Windowed Watchdog Reaction. |
RTI_WWDSIZECTRL is shown in Figure 12-2880 and described in Table 12-5506.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00A8h |
RTI1_CFG | 0221 00A8h |
RTI28_CFG | 023C 00A8h |
RTI29_CFG | 023D 00A8h |
MCU_RTI0_CFG | 4060 00A8h |
MCU_RTI1_CFG | 4061 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WWDSIZE | |||||||||||||||||||||||||||||||
R/W-5h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WWDSIZE | R/W | 5h | Digital Windowed Watchdog Window Size. |
RTI_INTCLRENABLE is shown in Figure 12-2881 and described in Table 12-5508.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00ACh |
RTI1_CFG | 0221 00ACh |
RTI28_CFG | 023C 00ACh |
RTI29_CFG | 023D 00ACh |
MCU_RTI0_CFG | 4060 00ACh |
MCU_RTI1_CFG | 4061 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | INTCLRENABLE3 | ||||||
R-0h | R/W-5h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | INTCLRENABLE2 | ||||||
R-0h | R/W-5h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INTCLRENABLE1 | ||||||
R-0h | R/W-5h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTCLRENABLE0 | ||||||
R-0h | R/W-5h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-24 | INTCLRENABLE3 | R/W | 5h | Enables the auto-clear functionality on the compare 3 interrupt. |
23-20 | RESERVED | R | 0h | Reserved |
19-16 | INTCLRENABLE2 | R/W | 5h | Enables the auto-clear functionality on the compare 2 interrupt. |
15-12 | RESERVED | R | 0h | Reserved |
11-8 | INTCLRENABLE1 | R/W | 5h | Enables the auto-clear functionality on the compare 1 interrupt. |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | INTCLRENABLE0 | R/W | 5h | Enables the auto-clear functionality on the compare 0 interrupt. |
RTI_COMP0CLR is shown in Figure 12-2882 and described in Table 12-5510.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00B0h |
RTI1_CFG | 0221 00B0h |
RTI28_CFG | 023C 00B0h |
RTI29_CFG | 023D 00B0h |
MCU_RTI0_CFG | 4060 00B0h |
MCU_RTI1_CFG | 4061 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP0CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP0CLR | R/W | 0h | Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. |
RTI_COMP1CLR is shown in Figure 12-2883 and described in Table 12-5512.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00B4h |
RTI1_CFG | 0221 00B4h |
RTI28_CFG | 023C 00B4h |
RTI29_CFG | 023D 00B4h |
MCU_RTI0_CFG | 4060 00B4h |
MCU_RTI1_CFG | 4061 00B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP1CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP1CLR | R/W | 0h | Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 1 interrupt or DMA request line is cleared. |
RTI_COMP2CLR is shown in Figure 12-2884 and described in Table 12-5514.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00B8h |
RTI1_CFG | 0221 00B8h |
RTI28_CFG | 023C 00B8h |
RTI29_CFG | 023D 00B8h |
MCU_RTI0_CFG | 4060 00B8h |
MCU_RTI1_CFG | 4061 00B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP2CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP2CLR | R/W | 0h | Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 2 interrupt or DMA request line is cleared. |
RTI_COMP3CLR is shown in Figure 12-2885 and described in Table 12-5516.
Return to Summary Table.
Instance | Physical Address |
---|---|
RTI0_CFG | 0220 00BCh |
RTI1_CFG | 0221 00BCh |
RTI28_CFG | 023C 00BCh |
RTI29_CFG | 023D 00BCh |
MCU_RTI0_CFG | 4060 00BCh |
MCU_RTI1_CFG | 4061 00BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP3CLR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP3CLR | R/W | 0h | Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 3 interrupt or DMA request line is cleared. |