SPRUIU1C July   2020  – February 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Export Control Notice
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  Navigator Subsystem
      4. 1.3.4  Region-based Address Translation Module
      5. 1.3.5  Multicore Shared Memory Controller
      6. 1.3.6  DDR Subsystem
      7. 1.3.7  General Purpose Input/Output Interface
      8. 1.3.8  Inter-Integrated Circuit Interface
      9. 1.3.9  Improved Inter-Integrated Circuit Interface
      10. 1.3.10 Multi-channel Serial Peripheral Interface
      11. 1.3.11 Universal Asynchronous Receiver/Transmitter
      12. 1.3.12 Gigabit Ethernet Switch
      13. 1.3.13 Peripheral Component Interconnect Express Subsystem
      14. 1.3.14 Universal Serial Bus (USB) Subsystem
      15. 1.3.15 SerDes
      16. 1.3.16 General Purpose Memory Controller with Error Location Module
      17. 1.3.17 Multimedia Card/Secure Digital Interface
      18. 1.3.18 Enhanced Capture Module
      19. 1.3.19 Enhanced Pulse-Width Modulation Module
      20. 1.3.20 Enhanced Quadrature Encoder Pulse Module
      21. 1.3.21 Controller Area Network
      22. 1.3.22 Audio Tracking Logic
      23. 1.3.23 Multi-channel Audio Serial Port
      24. 1.3.24 Timers
      25. 1.3.25 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
      5. 3.3.5 Null Error Reporting
      6. 3.3.6 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.6.1 Overview and Feature List
          1. 3.3.6.1.1 Features Supported
          2. 3.3.6.1.2 Features Not Supported
        2. 3.3.6.2 Functional Description
          1. 3.3.6.2.1 Functional Operation
            1. 3.3.6.2.1.1  Overview
            2. 3.3.6.2.1.2  FIFOs
            3. 3.3.6.2.1.3  ID Allocator
            4. 3.3.6.2.1.4  Timer
            5. 3.3.6.2.1.5  Timeout Queue
            6. 3.3.6.2.1.6  Write Scoreboard
            7. 3.3.6.2.1.7  Read Scoreboard
            8. 3.3.6.2.1.8  Flush Mode
            9. 3.3.6.2.1.9  Flushing
            10. 3.3.6.2.1.10 Timeout Error Reporting
            11. 3.3.6.2.1.11 Command Timeout Error Reporting
            12. 3.3.6.2.1.12 Unexpected Response Reporting
            13. 3.3.6.2.1.13 Latency and Stalls
            14. 3.3.6.2.1.14 Bypass
            15. 3.3.6.2.1.15 Safety
        3. 3.3.6.3 Interrupt Conditions
          1. 3.3.6.3.1 Transaction Error Interrupt
            1. 3.3.6.3.1.1 Transaction Timeout
            2. 3.3.6.3.1.2 Unexpected Response
            3. 3.3.6.3.1.3 Command Timeout
        4. 3.3.6.4 Memory Map
          1. 3.3.6.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.6.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.6.4.3  Info Register (Base Address + 0x08)
          4. 3.3.6.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.6.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.6.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.6.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.6.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.6.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.6.5 Integration Overview
          1. 3.3.6.5.1 Parameterization Requirements
        6. 3.3.6.6 I/O Description
          1. 3.3.6.6.1 Clockstop Idle
          2. 3.3.6.6.2 Flush
          3. 3.3.6.6.3 Module I/O
        7. 3.3.6.7 User’s Guide
          1. 3.3.6.7.1 Programmer’s Guide
            1. 3.3.6.7.1.1 Initialization
            2. 3.3.6.7.1.2 Software Flush
      7. 3.3.7 Timeout Gasket (TOG)
    4. 3.4 System Interconnect Registers
      1. 3.4.1 QoS Registers
      2. 3.4.2 Firewall Exception Registers
      3. 3.4.3 Firewall Region Registers
      4. 3.4.4 Null Error Reporting Registers
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 HSDIV Values
        6. 4.3.16.6 190
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 226
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
        4. 5.1.1.4 WKUP_CTRL_MMR0 Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
        4. 5.1.2.4 MCU_CTRL_MMR0 Registers
        5. 5.1.2.5 MCU_SEC_MMR0_DBG_CTRL Registers
        6. 5.1.2.6 MCU_SEC_MMR0_BOOT_CTRL Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  Clock Muxing and Division Registers
            8. 5.1.3.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.3.3.1.9  SERDES Lane Function Control Registers
            10. 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
        4. 5.1.3.4 CTRL_MMR0 Registers
        5. 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
        6. 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Subsystems Overview
          1. 5.2.2.1.1 POK Overview
          2. 5.2.2.1.2 PRG / PRG_PP Overview
          3. 5.2.2.1.3 POR Overview
          4. 5.2.2.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.2.1.5 Timing
          6. 5.2.2.1.6 Restrictions
        2. 5.2.2.2 Power System Modules
          1. 5.2.2.2.1 Power OK (POK) Modules
            1. 5.2.2.2.1.1 POK Programming Model
              1. 5.2.2.2.1.1.1 POK Threshold Setting Programming Sequence
          2. 5.2.2.2.2 Power on Reset (POR) Module
            1. 5.2.2.2.2.1 POR Overview
            2. 5.2.2.2.2.2 POR Integration
            3. 5.2.2.2.2.3 POR Programming Model
          3. 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.2.2.3.1 PRG_PP Overview
            2. 5.2.2.2.3.2 PRG_PP Integration
            3. 5.2.2.2.3.3 PRG_PP Programming Model
          4. 5.2.2.2.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.2.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.2.5.1 VTM Overview
              1. 5.2.2.2.5.1.1 VTM Features
              2. 5.2.2.2.5.1.2 VTM Not Supported Features
            2. 5.2.2.2.5.2 VTM Integration
            3. 5.2.2.2.5.3 VTM Functional Description
              1. 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.2.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.2.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.2.5.3.4 VTM Clocking
              5. 5.2.2.2.5.3.5 VTM Retention Interface
              6. 5.2.2.2.5.3.6 VTM ECC Aggregator
              7. 5.2.2.2.5.3.7 VTM Programming Model
                1. 5.2.2.2.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.2.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.2.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.2.5.3.8 AVS-Class0
          6. 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
        3. 5.2.2.3 Power Control Modules
          1. 5.2.2.3.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.3.1.1 PSC Terminology
            2. 5.2.2.3.1.2 PSC Features
            3. 5.2.2.3.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.3.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.3.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.3.1.3.3 LPSC Dependences Overview
            4. 5.2.2.3.1.4 PSC: Power Domain and Module States
              1. 5.2.2.3.1.4.1 Power Domain States
              2. 5.2.2.3.1.4.2 Module States
              3. 5.2.2.3.1.4.3 Local Reset
            5. 5.2.2.3.1.5 PSC: Executing State Transitions
              1. 5.2.2.3.1.5.1 Power Domain State Transitions
              2. 5.2.2.3.1.5.2 Module State Transitions
              3. 5.2.2.3.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.3.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.3.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.3.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.3.1.7.2 A72SS Power State Transition
              3. 5.2.2.3.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.3.1.7.4 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              5. 5.2.2.3.1.7.5 MCU Cortex-R5F Power Modes
          2. 5.2.2.3.2 Integrated Power Management (DMSC)
            1. 5.2.2.3.2.1 DMSC Power Management Overview
              1. 5.2.2.3.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
          4. 5.2.3.6.4 DDRSS Self-Refresh
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
      6. 5.2.6 Registers
        1. 5.2.6.1 WKUP_VTM0 Registers
        2. 5.2.6.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 424
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 WKUP and MCU Domains PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLL Lock
              4. 5.4.5.4.1.2.4 HSDIVIDER
              5. 5.4.5.4.1.2.5 ICG Module
              6. 5.4.5.4.1.2.6 PLL Power Down
              7. 5.4.5.4.1.2.7 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Registers
        1. 5.4.6.1 MCU_PLL0_CFG Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 PLLCTRL0 Registers
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
      3. 6.1.3 Compute Cluster Registers
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
      4. 6.2.4 A72SS Registers
        1. 6.2.4.1 Arm A72 Cluster Registers
        2. 6.2.4.2 A72SS ECC Aggregator Registers
          1. 6.2.4.2.1 A72SS CLUSTER ECC Registers
          2. 6.2.4.2.2 A72SS CORE0 ECC Registers
          3. 6.2.4.2.3 A72SS CORE1 ECC Registers
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 R5FSS Master Interfaces
          2. 6.3.3.3.2 R5FSS Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
          1. 6.3.3.7.1 RAT Overview
          2. 6.3.3.7.2 RAT Operation
          3. 6.3.3.7.3 RAT Error Logging
          4. 6.3.3.7.4 RAT Protection
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Debug and Trace
        11. 6.3.3.11 R5FSS Boot Options
        12. 6.3.3.12 R5FSS Core Memory ECC Events
      4. 6.3.4 R5FSS Registers
        1. 6.3.4.1 R5FSS_CCMR5 Registers
        2. 6.3.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.3.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.3.4.4 R5FSS_VIM Registers
        5. 6.3.4.5 R5FSS_RAT Registers
        6. 6.3.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 639
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
      4. 8.1.4 MSMC Registers
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
      5. 8.2.5 DDRSS Registers
        1. 8.2.5.1 DDR Subsystem Registers
        2. 8.2.5.2 DDR Controller Registers
        3. 8.2.5.3 PI Registers
        4. 8.2.5.4 DDR PHY Registers
        5. 8.2.5.5 DDRSS0_ECC_AGGR_CTL Registers
        6. 8.2.5.6 DDRSS0_ECC_AGGR_VBUS Registers
        7. 8.2.5.7 DDRSS0_ECC_AGGR_CFG Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
        3. 8.3.1.3 PVU Not Supported Features
      2. 8.3.2 PVU Integration
      3. 8.3.3 PVU Functional Description
        1. 8.3.3.1  Functional Operation Overview
        2. 8.3.3.2  PVU Channels
        3. 8.3.3.3  TLB
        4. 8.3.3.4  TLB Entry
        5. 8.3.3.5  TLB Selection
        6. 8.3.3.6  DMA Classes
        7. 8.3.3.7  General virtIDs
        8. 8.3.3.8  TLB Lookup
        9. 8.3.3.9  TLB Miss
        10. 8.3.3.10 Multiple Matching Entries
        11. 8.3.3.11 TLB Disable
        12. 8.3.3.12 TLB Chaining
        13. 8.3.3.13 TLB Permissions
        14. 8.3.3.14 Translation
        15. 8.3.3.15 Memory Attributes
        16. 8.3.3.16 Faulted Transactions
        17. 8.3.3.17 Non-Virtual Transactions
        18. 8.3.3.18 Allowed virtIDs
        19. 8.3.3.19 Software Control
        20. 8.3.3.20 Fault Logging
        21. 8.3.3.21 Alignment Restrictions
      4. 8.3.4 PVU Registers
        1. 8.3.4.1 NAVSS_PVU_CFG Registers
        2. 8.3.4.2 NAVSS0_PVU_CFG_TLBIF Registers
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
      2. 8.4.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GIC Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GIC_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 WKUP_GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 GPIOMUX_INTRTR0 Registers
        3. 9.3.3.3 MAIN2MCU_LVL_INTRTR0 Registers
        4. 9.3.3.4 MAIN2MCU_PLS_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_GPIO0_VIRT Interrupt Map
        4. 9.4.1.4 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1 COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
          3. 9.4.3.1.3 SoC Event Output Interrupt Map
        2. 9.4.3.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        5. 9.4.3.5 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        6. 9.4.3.6 GPIOMUX_INTRTR0 Interrupt Map
        7. 9.4.3.7 GPIO0_VIRT Interrupt Map
        8. 9.4.3.8 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA External Transmit Channel Setup
        6. 10.1.3.6  UDMA Transmit External Channel Teardown
        7. 10.1.3.7  UDMA-P Transmit Channel Pause
        8. 10.1.3.8  UDMA-P Transmit Operation (Host Packet Type)
        9. 10.1.3.9  UDMA-P Transmit Operation (Monolithic Packet)
        10. 10.1.3.10 UDMA Transmit Operation (TR Packet)
        11. 10.1.3.11 UDMA Transmit Operation (Direct TR)
        12. 10.1.3.12 UDMA Transmit Error/Exception Handling
          1. 10.1.3.12.1 Null Icnt0 Error
          2. 10.1.3.12.2 Unsupported TR Type
          3. 10.1.3.12.3 Bus Errors
        13. 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
        14. 10.1.3.14 UDMA Receive Channel Teardown
        15. 10.1.3.15 UDMA-P Receive Channel Pause
        16. 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        17. 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
        18. 10.1.3.18 UDMA-P Receive Operation (Host Packet)
        19. 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
        20. 10.1.3.20 UDMA Receive Operation (TR Packet)
        21. 10.1.3.21 UDMA Receive Operation (Direct TR)
        22. 10.1.3.22 UDMA Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Conditions
            1. 10.1.3.22.1.1 Bus Errors
            2. 10.1.3.22.1.2 Null Icnt0 Error
            3. 10.1.3.22.1.3 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions Exception Conditions
            1. 10.1.3.22.2.1 Descriptor Starvation
            2. 10.1.3.22.2.2 Protocol Errors
            3. 10.1.3.22.2.3 Dropped Packets
            4. 10.1.3.22.2.4 Reception of EOL Delimiter
            5. 10.1.3.22.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.22.2.6 EOP Asserted Late (Long Packets)
        23. 10.1.3.23 UTC Operation
        24. 10.1.3.24 UTC Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Handling
            1. 10.1.3.24.1.1 Null Icnt0 Error
            2. 10.1.3.24.1.2 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions
            1. 10.1.3.24.2.1 Reception of EOL Delimiter
            2. 10.1.3.24.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.24.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
        5. 10.2.1.5 NAVSS Top-level Registers
          1. 10.2.1.5.1 NAVSS0_CFG Registers
          2. 10.2.1.5.2 INTR0_INTR_ROUTER_CFG Registers
          3. 10.2.1.5.3 VIRTID_CFG_MMRS Registers
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1006
        3. 10.2.2.3 MCU NAVSS Functional Description
        4. 10.2.2.4 MCU NAVSS Top-Level Registers
          1. 10.2.2.4.1 MCU_NAVSS0_CFG Registers
          2. 10.2.2.4.2 MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
        4. 10.2.3.4 UDMA Registers
          1. 10.2.3.4.1 UDMASS_UDMAP0_CFG Registers
          2. 10.2.3.4.2 UDMASS_UDMAP0_CFG_TCHAN Registers
          3. 10.2.3.4.3 UDMASS_UDMAP0_CFG_RCHAN Registers
          4. 10.2.3.4.4 UDMASS_UDMAP0_CFG_RFLOW Registers
          5. 10.2.3.4.5 UDMASS_UDMAP0_CFG_RCHANRT Registers
          6. 10.2.3.4.6 UDMASS_UDMAP0_CFG_TCHANRT Registers
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
        4. 10.2.4.4 RINGACC Registers
          1. 10.2.4.4.1 NAVSS0_UDMASS_RINGACC0_CFG Registers
          2. 10.2.4.4.2 NAVSS0_UDMASS_RINGACC0_GCFG Registers
          3. 10.2.4.4.3 NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
          4. 10.2.4.4.4 NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
          5. 10.2.4.4.5 NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
        4. 10.2.5.4 Proxy Registers
          1. 10.2.5.4.1 NAVSS0_PROXY0_CFG_BUF_CFG Registers
          2. 10.2.5.4.2 NAVSS0_PROXY0_BUF_CFG Registers
          3. 10.2.5.4.3 NAVSS0_PROXY_BUF Registers
          4. 10.2.5.4.4 NAVSS0_PROXY_TARGET0_DATA Registers
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
        4. 10.2.6.4 Secure Proxy Registers
          1. 10.2.6.4.1 NAVSS0_SEC_PROXY0_CFG_MMRS Registers
          2. 10.2.6.4.2 NAVSS0_SEC_PROXY0_CFG_RT Registers
          3. 10.2.6.4.3 NAVSS0_SEC_PROXY0_CFG_SCFG Registers
          4. 10.2.6.4.4 NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
        4. 10.2.7.4 INTR_AGGR Registers
          1. 10.2.7.4.1  MODSS_INTA_CFG Registers
          2. 10.2.7.4.2  MODSS_INTA_CFG_IMAP Registers
          3. 10.2.7.4.3  MODSS_INTA_CFG_INTR Registers
          4. 10.2.7.4.4  UDMASS_INTA0_CFG Registers
          5. 10.2.7.4.5  UDMASS_INTA0_CFG_INTR Registers
          6. 10.2.7.4.6  UDMASS_INTA0_CFG_IMAP Registers
          7. 10.2.7.4.7  UDMASS_INTA0_CFG_L2G Registers
          8. 10.2.7.4.8  UDMASS_INTA0_CFG_MCAST Registers
          9. 10.2.7.4.9  UDMASS_INTA0_CFG_GCNTCFG Registers
          10. 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
        3. 10.2.8.3 PSI-L Configuration Registers
        4. 10.2.8.4 PSI-L CFG_PROXY Registers
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
        3. 10.2.9.3 PSILSS Registers
          1. 10.2.9.3.1 PDMA_USART_PSILSS0 Registers
          2. 10.2.9.3.2 PDMA_SPI_PSILSS0 Registers
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
        3. 10.2.10.3 NB Registers
          1. 10.2.10.3.1 NAVSS0_NBSS_CFG_REGS0_MMRS Registers
          2. 10.2.10.3.2 NAVSS0_NBSS_NB_CFG_MMRS Registers
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA2 (PDMA_DEBUG_CCMCU) Features
            6. 10.3.1.1.1.6  PDMA5 (PDMA_MCAN) Features
            7. 10.3.1.1.1.7  PDMA6 (PDMA_MCASP_G0) Features
            8. 10.3.1.1.1.8  PDMA9 (PDMA_SPI_G0) Features
            9. 10.3.1.1.1.9  PDMA10 (PDMA_SPI_G1) Features
            10. 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
            11. 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
            12. 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1288
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1297
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
        4. 10.3.1.4 PDMA Registers
          1. 10.3.1.4.1 PDMA5 ECC Registers
          2. 10.3.1.4.2 PDMA9 ECC Registers
          3. 10.3.1.4.3 PDMA10 ECC Registers
          4. 10.3.1.4.4 PDMA PSI-L TX Configuration Registers
          5. 10.3.1.4.5 PDMA PSI-L RX Configuration Registers
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_DEBUG_CCMCU Event Map
          2. 10.3.2.2.2 PDMA_MCAN Event Map
          3. 10.3.2.2.3 PDMA_MCASP_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G0 Event Map
          5. 10.3.2.2.5 PDMA_SPI_G1 Event Map
          6. 10.3.2.2.6 PDMA_USART_G0 Event Map
          7. 10.3.2.2.7 PDMA_USART_G1 Event Map
          8. 10.3.2.2.8 PDMA_USART_G2 Event Map
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
      4. 11.1.4 CPTS Registers
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
      5. 11.2.5 Timer Manager Registers
        1. 11.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 11.2.5.2 TIMERMGR_CFG_OES Registers
        3. 11.2.5.3 TIMERMGR_CFG_TIMERS Registers
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
        2. 11.3.2.2 Time Sync Routers Integration
          1. 11.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 11.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 11.3.2.3 Time Sync Routers Registers
          1. 11.3.2.3.1 TIMESYNC_INTRTR0 Registers
          2. 11.3.2.3.2 CMPEVT_INTRTR0 Registers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1 CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2 TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3 DMSS0 Sync Event Map
        4. 11.3.3.4 PCIE1 Sync Event Map
        5. 11.3.3.5 MCU_CPSW0 Sync Event Map
        6. 11.3.3.6 CPSW0 Sync Event Map
        7. 11.3.3.7 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1501
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1555
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
        6. 12.1.4.6 I3C Registers
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.5.6 MCSPI Registers
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
        6. 12.1.6.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 1945
                1. 12.2.1.4.6.10.1.1 1946
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2045
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2073
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 MCU_CPSW0 Registers
          1. 12.2.1.6.1  MCU_CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  MCU_CPSW0_SGMII Registers
          3. 12.2.1.6.3  MCU_CPSW0_MDIO Registers
          4. 12.2.1.6.4  MCU_CPSW0_CPTS Registers
          5. 12.2.1.6.5  MCU_CPSW0_CONTROL Registers
          6. 12.2.1.6.6  MCU_CPSW0_CPINT Registers
          7. 12.2.1.6.7  MCU_CPSW0_RAM Registers
          8. 12.2.1.6.8  MCU_CPSW0_STAT0 Registers
          9. 12.2.1.6.9  MCU_CPSW0_STAT1 Registers
          10. 12.2.1.6.10 MCU_CPSW0_ALE Registers
          11. 12.2.1.6.11 MCU_CPSW0_ECC Registers
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_5X
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2324
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2352
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
        6. 12.2.2.6 CPSW0 Registers
          1. 12.2.2.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.2.6.2  CPSW0_SGMII Registers
          3. 12.2.2.6.3  CPSW0_MDIO Registers
          4. 12.2.2.6.4  CPSW0_CPTS Registers
          5. 12.2.2.6.5  CPSW0_CONTROL Registers
          6. 12.2.2.6.6  CPSW0_CPINT Registers
          7. 12.2.2.6.7  CPSW0_RAM Registers
          8. 12.2.2.6.8  CPSW0_STAT Registers
          9. 12.2.2.6.9  CPSW0_ALE Registers
          10. 12.2.2.6.10 CPSW0_PCSR Registers
          11. 12.2.2.6.11 CPSW0_ECC Registers
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Conventional Reset
            2. 12.2.3.4.2.2 PCIe Function Level Reset
            3. 12.2.3.4.2.3 PCIe Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupts Aggregation
            2. 12.2.3.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.3.5 PTM Valid Interrupt
            4. 12.2.3.4.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.4.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.4.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.4.4.6.1 PCIe Local Interrupt
              2. 12.2.3.4.4.6.2 PHY Interrupt
              3. 12.2.3.4.4.6.3 Link down Interrupt
              4. 12.2.3.4.4.6.4 Transaction Error Interrupts
              5. 12.2.3.4.4.6.5 Power Management Event Interrupt
              6. 12.2.3.4.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.4.4.7 ECC Aggregator Interrupts
            8. 12.2.3.4.4.8 CPTS Interrupt
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.4.6  PCIe Subsystem Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 End Point SR-IOV Support
            2. 12.2.3.4.8.2 Root Port ATS Support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC Inversion
          14. 12.2.3.4.14 LTSSM State Encoding
        5. 12.2.3.5 PCIe Subsystem Registers
          1. 12.2.3.5.1  PCIE_CORE_EP_PF Registers
          2. 12.2.3.5.2  PCIE_CORE_EP_VF Registers
          3. 12.2.3.5.3  PCIE_CORE_RP Registers
          4. 12.2.3.5.4  PCIE_CORE_LM Registers
          5. 12.2.3.5.5  PCIE_CORE_AXI Registers
          6. 12.2.3.5.6  PCIE_INTD Registers
          7. 12.2.3.5.7  PCIE_VMAP Registers
          8. 12.2.3.5.8  PCIE_CPTS Registers
          9. 12.2.3.5.9  PCIE_USER_CFG Registers
          10. 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
          11. 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
          12. 12.2.3.5.12 PCIE_DAT0 Registers
          13. 12.2.3.5.13 PCIE_DAT1 Registers
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB_RAMS_INJ_CFG Registers
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Integration
          1. 12.2.5.3.1 WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Reference Clock Distribution
            3. 12.2.5.3.1.3 Internal Reference Clock Selection
        4. 12.2.5.4 SerDes Functional Description
          1. 12.2.5.4.1 SerDes Block Diagram
          2. 12.2.5.4.2 SerDes Programming Guide
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Regions
            1. 12.3.1.4.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.4.5 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
        6. 12.3.1.6 FSS Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2576
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        6. 12.3.2.6 OSPI Registers
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
        6. 12.3.3.6 HyperBus Registers
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.4.6 GPMC Registers
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 2786
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.5.5 ELM Registers
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 2865
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.6.6 MMCSD Registers
          1. 12.3.6.6.1 MMCSD0 Subsystem Registers
          2. 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.6.6.4 MMCSD0 Host Controller Registers
          5. 12.3.6.6.5 MMCSD1 Subsystem Registers
          6. 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.6.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.1.6 ECAP Registers
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 2951
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 2964
            3. 12.4.2.4.2.3 Controlling and Monitoring the EPWM Time-Base Submodule
            4. 12.4.2.4.2.4 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.4.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.4.2 EPWM Time-Base Counter Synchronization
            5. 12.4.2.4.2.5 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            6. 12.4.2.4.2.6 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 2987
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3002
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.2.5 EPWM Registers
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
        5. 12.4.3.5 EQEP Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3064
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
        5. 12.4.4.5 MCAN Registers
          1. 12.4.4.5.1 MCAN Subsystem Registers
          2. 12.4.4.5.2 MCAN Core Registers
          3. 12.4.4.5.3 MCAN ECC Aggregator Registers
    5. 12.5 Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
    6. 12.6 Timer Modules
      1. 12.6.1 Global Timebase Counter (GTC)
        1. 12.6.1.1 GTC Overview
          1. 12.6.1.1.1 GTC Features
          2. 12.6.1.1.2 GTC Not Supported Features
        2. 12.6.1.2 GTC Integration
        3. 12.6.1.3 GTC Functional Description
          1. 12.6.1.3.1 GTC Block Diagram
          2. 12.6.1.3.2 GTC Counter
          3. 12.6.1.3.3 GTC Gray Encoder
          4. 12.6.1.3.4 GTC Push Event Generation
          5. 12.6.1.3.5 GTC Register Partitioning
        4. 12.6.1.4 GTC Registers
          1. 12.6.1.4.1 GTC0_GTC_CFG0 Registers
          2. 12.6.1.4.2 GTC0_GTC_CFG1 Registers
          3. 12.6.1.4.3 GTC0_GTC_CFG2 Registers
          4. 12.6.1.4.4 GTC0_GTC_CFG3 Registers
      2. 12.6.2 Windowed Watchdog Timer (WWDT)
        1. 12.6.2.1 RTI Overview
          1. 12.6.2.1.1 RTI Features
          2. 12.6.2.1.2 RTI Not Supported Features
        2. 12.6.2.2 RTI Integration
          1. 12.6.2.2.1 RTI Integration in MCU Domain
          2. 12.6.2.2.2 RTI Integration in MAIN Domain
        3. 12.6.2.3 RTI Functional Description
          1. 12.6.2.3.1 RTI Counter Operation
          2. 12.6.2.3.2 RTI Digital Watchdog
          3. 12.6.2.3.3 RTI Digital Windowed Watchdog
          4. 12.6.2.3.4 RTI Low Power Mode Operation
          5. 12.6.2.3.5 RTI Debug Mode Behavior
        4. 12.6.2.4 RTI Registers
      3. 12.6.3 Timers
        1. 12.6.3.1 Timers Overview
          1. 12.6.3.1.1 Timers Features
          2. 12.6.3.1.2 Timers Not Supported Features
        2. 12.6.3.2 Timers Environment
          1. 12.6.3.2.1 Timer External System Interface
        3. 12.6.3.3 Timers Integration
          1. 12.6.3.3.1 Timers Integration in MCU Domain
          2. 12.6.3.3.2 Timers Integration in MAIN Domain
        4. 12.6.3.4 Timers Functional Description
          1. 12.6.3.4.1  Timer Block Diagram
          2. 12.6.3.4.2  Timer Power Management
            1. 12.6.3.4.2.1 Wake-Up Capability
          3. 12.6.3.4.3  Timer Software Reset
          4. 12.6.3.4.4  Timer Interrupts
          5. 12.6.3.4.5  Timer Mode Functionality
            1. 12.6.3.4.5.1 1-ms Tick Generation
          6. 12.6.3.4.6  Timer Capture Mode Functionality
          7. 12.6.3.4.7  Timer Compare Mode Functionality
          8. 12.6.3.4.8  Timer Prescaler Functionality
          9. 12.6.3.4.9  Timer Pulse-Width Modulation
          10. 12.6.3.4.10 Timer Counting Rate
          11. 12.6.3.4.11 Timer Under Emulation
          12. 12.6.3.4.12 Accessing Timer Registers
            1. 12.6.3.4.12.1 Writing to Timer Registers
              1. 12.6.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.6.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.6.3.4.12.2 Reading From Timer Counter Registers
              1. 12.6.3.4.12.2.1 Read Posted
              2. 12.6.3.4.12.2.2 Read Non-Posted
          13. 12.6.3.4.13 Timer Posted Mode Selection
        5. 12.6.3.5 Timers Low-Level Programming Models
          1. 12.6.3.5.1 Timer Global Initialization
            1. 12.6.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.6.3.5.1.2 Timer Module Global Initialization
              1. 12.6.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.6.3.5.2 Timer Operational Mode Configuration
            1. 12.6.3.5.2.1 Timer Mode
              1. 12.6.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.6.3.5.2.2 Timer Compare Mode
              1. 12.6.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.6.3.5.2.3 Timer Capture Mode
              1. 12.6.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.6.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.6.3.5.2.3.3 Subsequence – Detect Event
            4. 12.6.3.5.2.4 Timer PWM Mode
              1. 12.6.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.6.3.6 Timers Registers
    7. 12.7 Internal Diagnostics Modules
      1. 12.7.1 Dual Clock Comparator (DCC)
        1. 12.7.1.1 DCC Overview
          1. 12.7.1.1.1 DCC Features
          2. 12.7.1.1.2 DCC Not Supported Features
        2. 12.7.1.2 DCC Integration
          1. 12.7.1.2.1 DCC Integration in MCU Domain
          2. 12.7.1.2.2 DCC Integration in MAIN Domain
        3. 12.7.1.3 DCC Functional Description
          1. 12.7.1.3.1 DCC Counter Operation
          2. 12.7.1.3.2 DCC Low Power Mode Operation
          3. 12.7.1.3.3 DCC Suspend Mode Behavior
          4. 12.7.1.3.4 DCC Single-Shot Mode
          5. 12.7.1.3.5 DCC Continuous mode
            1. 12.7.1.3.5.1 DCC Continue on Error
            2. 12.7.1.3.5.2 DCC Error Count
          6. 12.7.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.7.1.3.7 DCC Error Trajectory record
            1. 12.7.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.7.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.7.1.3.7.3 DCC FIFO Details
            4. 12.7.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.7.1.3.8 DCC Count read registers
        4. 12.7.1.4 DCC Registers
      2. 12.7.2 Error Signaling Module (ESM)
        1. 12.7.2.1 ESM Overview
          1. 12.7.2.1.1 ESM Features
        2. 12.7.2.2 ESM Environment
        3. 12.7.2.3 ESM Integration
          1. 12.7.2.3.1 ESM Integration in WKUP Domain
          2. 12.7.2.3.2 ESM Integration in MCU Domain
          3. 12.7.2.3.3 ESM Integration in MAIN Domain
        4. 12.7.2.4 ESM Functional Description
          1. 12.7.2.4.1 ESM Interrupt Requests
            1. 12.7.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.7.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.7.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.7.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.7.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.7.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.7.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.7.2.4.2 ESM Error Event Inputs
          3. 12.7.2.4.3 ESM Error Pin Output
          4. 12.7.2.4.4 ESM Minimum Time Interval
          5. 12.7.2.4.5 ESM Protection for Registers
          6. 12.7.2.4.6 ESM Clock Stop
        5. 12.7.2.5 ESM Registers
      3. 12.7.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.7.3.1 MCRC Overview
          1. 12.7.3.1.1 MCRC Features
          2. 12.7.3.1.2 MCRC Not Supported Features
        2. 12.7.3.2 MCRC Integration
        3. 12.7.3.3 MCRC Functional Description
          1. 12.7.3.3.1  MCRC Block Diagram
          2. 12.7.3.3.2  MCRC General Operation
          3. 12.7.3.3.3  MCRC Modes of Operation
            1. 12.7.3.3.3.1 AUTO Mode
            2. 12.7.3.3.3.2 Semi-CPU Mode
            3. 12.7.3.3.3.3 Full-CPU Mode
          4. 12.7.3.3.4  PSA Signature Register
          5. 12.7.3.3.5  PSA Sector Signature Register
          6. 12.7.3.3.6  CRC Value Register
          7. 12.7.3.3.7  Raw Data Register
          8. 12.7.3.3.8  Example DMA Controller Setup
            1. 12.7.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.7.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.7.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.7.3.3.9  Pattern Count Register
          10. 12.7.3.3.10 Sector Count Register/Current Sector Register
          11. 12.7.3.3.11 Interrupts
            1. 12.7.3.3.11.1 Compression Complete Interrupt
            2. 12.7.3.3.11.2 CRC Fail Interrupt
            3. 12.7.3.3.11.3 Overrun Interrupt
            4. 12.7.3.3.11.4 Underrun Interrupt
            5. 12.7.3.3.11.5 Timeout Interrupt
            6. 12.7.3.3.11.6 Interrupt Offset Register
            7. 12.7.3.3.11.7 Error Handling
          12. 12.7.3.3.12 Power Down Mode
          13. 12.7.3.3.13 Emulation
        4. 12.7.3.4 MCRC Programming Examples
          1. 12.7.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.7.3.4.1.1 DMA Setup
            2. 12.7.3.4.1.2 Timer Setup
            3. 12.7.3.4.1.3 CRC Setup
          2. 12.7.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.7.3.4.2.1 DMA Setup
            2. 12.7.3.4.2.2 CRC Setup
          3. 12.7.3.4.3 Example: Semi-CPU Mode
            1. 12.7.3.4.3.1 DMA Setup
            2. 12.7.3.4.3.2 Timer Setup
            3. 12.7.3.4.3.3 CRC Setup
          4. 12.7.3.4.4 Example: Full-CPU Mode
            1. 12.7.3.4.4.1 CRC Setup
        5. 12.7.3.5 MCRC Registers
      4. 12.7.4 ECC Aggregator
        1. 12.7.4.1 ECC Aggregator Overview
          1. 12.7.4.1.1 ECC Aggregator Features
        2. 12.7.4.2 ECC Aggregator Integration
        3. 12.7.4.3 ECC Aggregator Functional Description
          1. 12.7.4.3.1 ECC Aggregator Block Diagram
          2. 12.7.4.3.2 ECC Aggregator Register Groups
          3. 12.7.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.7.4.3.4 Serial Write Operation
          5. 12.7.4.3.5 Interrupts
          6. 12.7.4.3.6 Inject Only Mode
        4. 12.7.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
  16. 14Revision History
12.2.3.5.1 PCIE_CORE_EP_PF Registers

Table 12-3458 lists the PCIE_CORE_EP_PF registers. All register offset addresses not listed in Table 12-3458 should be considered as reserved locations and the register contents should not be modified.

EP mode physical function (PF) PCIE core registers. There are 6 Physical Functions, which are assigned to function numbers 0 through 5.

Table 12-2469 PCIE_CORE_EP_PF Instances
InstanceBase Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0000h
Table 12-2470 PCIE_CORE_EP_PF Registers
Offset Acronym Register Name PCIE1_CORE_DBN_CFG_PCIE_CORE
Physical Address
0h + formula PCIE_CORE_PFn_I_VENDOR_ID_DEVICE_ID 0D80 0000h + formula
4h + formula PCIE_CORE_PFn_I_COMMAND_STATUS 0D80 0004h + formula
8h + formula PCIE_CORE_PFn_I_REVISION_ID_CLASS_CODE 0D80 0008h + formula
Ch + formula PCIE_CORE_PFn_I_BIST_HEADER_LATENCY_CACHE_LINE 0D80 000Ch + formula
10h + formula PCIE_CORE_PFn_I_BASE_ADDR_0 0D80 0010h + formula
14h + formula PCIE_CORE_PFn_I_BASE_ADDR_1 0D80 0014h + formula
18h + formula PCIE_CORE_PFn_I_BASE_ADDR_2 0D80 0018h + formula
1Ch + formula PCIE_CORE_PFn_I_BASE_ADDR_3 0D80 001Ch + formula
20h + formula PCIE_CORE_PFn_I_BASE_ADDR_4 0D80 0020h + formula
24h + formula PCIE_CORE_PFn_I_BASE_ADDR_5 0D80 0024h + formula
28h + formula PCIE_CORE_PFn_RSVD_0A 0D80 0028h + formula
2Ch + formula PCIE_CORE_PFn_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I 0D80 002Ch + formula
30h + formula PCIE_CORE_PFn_RSVD_0C 0D80 0030h + formula
34h + formula PCIE_CORE_PFn_I_CAPABILITIES_POINTER 0D80 0034h + formula
38h + formula PCIE_CORE_PFn_RSVD_0E 0D80 0038h + formula
3Ch + formula PCIE_CORE_PFn_I_INTRPT_LINE_INTRPT_PIN 0D80 003Ch + formula
40h + formula PCIE_CORE_PFn_RSVD_010_01F 0D80 0040h + formula
80h + formula PCIE_CORE_PFn_I_PWR_MGMT_CAP 0D80 0080h + formula
84h + formula PCIE_CORE_PFn_I_PWR_MGMT_CTRL_STAT_REP 0D80 0084h + formula
88h + formula PCIE_CORE_PFn_RSVD_022_023 0D80 0088h + formula
90h + formula PCIE_CORE_PFn_I_MSI_CTRL_REG 0D80 0090h + formula
94h + formula PCIE_CORE_PFn_I_MSI_MSG_LOW_ADDR 0D80 0094h + formula
98h + formula PCIE_CORE_PFn_I_MSI_MSG_HI_ADDR 0D80 0098h + formula
9Ch + formula PCIE_CORE_PFn_I_MSI_MSG_DATA 0D80 009Ch + formula
A0h + formula PCIE_CORE_PFn_I_MSI_MASK 0D80 00A0h + formula
A4h + formula PCIE_CORE_PFn_I_MSI_PENDING_BITS 0D80 00A4h + formula
A8h + formula PCIE_CORE_PFn_RSVD_02A_02B 0D80 00A8h + formula
B0h + formula PCIE_CORE_PFn_I_MSIX_CTRL 0D80 00B0h + formula
B4h + formula PCIE_CORE_PFn_I_MSIX_TBL_OFFSET 0D80 00B4h + formula
B8h + formula PCIE_CORE_PFn_I_MSIX_PENDING_INTRPT 0D80 00B8h + formula
BCh + formula PCIE_CORE_PFn_RSVD_02F 0D80 00BCh + formula
C0h + formula PCIE_CORE_PFn_I_PCIE_CAP_LIST 0D80 00C0h + formula
C4h + formula PCIE_CORE_PFn_I_PCIE_DEV_CAP 0D80 00C4h + formula
C8h + formula PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS 0D80 00C8h + formula
CCh + formula PCIE_CORE_PFn_I_LINK_CAP 0D80 00CCh + formula
D0h + formula PCIE_CORE_PFn_I_LINK_CTRL_STATUS 0D80 00D0h + formula
D4h + formula PCIE_CORE_PFn_RSVD_035 0D80 00D4h + formula
D8h + formula PCIE_CORE_PFn_RSVD_036 0D80 00D8h + formula
DCh + formula PCIE_CORE_PFn_RSVD_037_038 0D80 00DCh + formula
E4h + formula PCIE_CORE_PFn_I_PCIE_DEV_CAP_2 0D80 00E4h + formula
E8h + formula PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS_2 0D80 00E8h + formula
ECh + formula PCIE_CORE_PFn_I_LINK_CAP_2_REG 0D80 00ECh + formula
F0h + formula PCIE_CORE_PFn_I_LINK_CTRL_STATUS_2 0D80 00F0h + formula
F4h + formula PCIE_CORE_PFn_RSVD_03D_03F 0D80 00F4h + formula
100h + formula PCIE_CORE_PFn_I_AER_ENHANCED_CAP_HDR 0D80 0100h + formula
104h + formula PCIE_CORE_PFn_I_UNCORR_ERR_STATUS 0D80 0104h + formula
108h + formula PCIE_CORE_PFn_I_UNCORR_ERR_MASK 0D80 0108h + formula
10Ch + formula PCIE_CORE_PFn_I_UNCORR_ERR_SEVERITY 0D80 010Ch + formula
110h + formula PCIE_CORE_PFn_I_CORR_ERR_STATUS 0D80 0110h + formula
114h + formula PCIE_CORE_PFn_I_CORR_ERR_MASK 0D80 0114h + formula
118h + formula PCIE_CORE_PFn_I_ADVCD_ERR_CAP_CTRL 0D80 0118h + formula
11Ch + formula PCIE_CORE_PFn_I_HDR_LOG_0 0D80 011Ch + formula
120h + formula PCIE_CORE_PFn_I_HDR_LOG_1 0D80 0120h + formula
124h + formula PCIE_CORE_PFn_I_HDR_LOG_2 0D80 0124h + formula
128h + formula PCIE_CORE_PFn_I_HDR_LOG_3 0D80 0128h + formula
12Ch + formula PCIE_CORE_PFn_RSVD_04B_04D 0D80 012Ch + formula
138h + formula PCIE_CORE_PFn_I_TLP_PRE_LOG_0 0D80 0138h + formula
140h + formula PCIE_CORE_PFn_I_ARI_EXT_CAP_HDR 0D80 0140h + formula
144h + formula PCIE_CORE_PFn_I_ARI_CAP_AND_CTRL 0D80 0144h + formula
148h + formula PCIE_CORE_PFn_RSVD_052_053 0D80 0148h + formula
150h + formula PCIE_CORE_PFn_I_DEV_SER_NUM_CAP_HDR 0D80 0150h + formula
154h + formula PCIE_CORE_PFn_I_DEV_SER_NUM_0 0D80 0154h + formula
158h + formula PCIE_CORE_PFn_I_DEV_SER_NUM_1 0D80 0158h + formula
15Ch + formula PCIE_CORE_PFn_RSVD_057 0D80 015Ch + formula
160h + formula PCIE_CORE_PFn_I_PWR_BDGTG_ENHC_CAP_HDR 0D80 0160h + formula
164h + formula PCIE_CORE_PFn_I_PWR_BDGTG_DATA_SEL 0D80 0164h + formula
168h + formula PCIE_CORE_PFn_I_PWR_BDGTG_DATA_REGISTER 0D80 0168h + formula
16Ch + formula PCIE_CORE_PFn_I_PWR_BDGT_CAP 0D80 016Ch + formula
170h + formula PCIE_CORE_PFn_RSVD_05C_05F 0D80 0170h + formula
180h + formula PCIE_CORE_PFn_I_RESIZE_BAR_EXT_CAP_HDR 0D80 0180h + formula
184h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CAP_0 0D80 0184h + formula
188h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_0 0D80 0188h + formula
18Ch + formula PCIE_CORE_PFn_I_RESIZE_BAR_CAP_1 0D80 018Ch + formula
190h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_1 0D80 0190h + formula
194h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CAP_2 0D80 0194h + formula
198h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_2 0D80 0198h + formula
19Ch + formula PCIE_CORE_PFn_I_RESIZE_BAR_CAP_3 0D80 019Ch + formula
1A0h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_3 0D80 01A0h + formula
1A4h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CAP_4 0D80 01A4h + formula
1A8h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_4 0D80 01A8h + formula
1ACh + formula PCIE_CORE_PFn_I_RESIZE_BAR_CAP_5 0D80 01ACh + formula
1B0h + formula PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_5 0D80 01B0h + formula
1B8h PCIE_CORE_PF0_I_LTR_EXT_CAP_HDR 0D80 01B8h
1BCh PCIE_CORE_PF0_I_LTR_SNOOP_LAT 0D80 01BCh
1C0h + formula PCIE_CORE_PFn_I_DPA_EXT_CAP_HEADER_REG 0D80 01C0h + formula
1C4h + formula PCIE_CORE_PFn_I_DPA_CAP_REG 0D80 01C4h + formula
1C8h + formula PCIE_CORE_PFn_I_DPA_LAT_INDICATOR_REG 0D80 01C8h + formula
1CCh + formula PCIE_CORE_PFn_I_DPA_CTRL_STATUS_REG 0D80 01CCh + formula
1D0h + formula PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG0 0D80 01D0h + formula
1D4h + formula PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG1 0D80 01D4h + formula
1D8h + formula PCIE_CORE_PFn_RSVD_07C_07F 0D80 01D8h + formula
200h + formula PCIE_CORE_PFn_I_SRIOV_EXT_CAP_HEADER_REG 0D80 0200h + formula
204h + formula PCIE_CORE_PFn_I_SRIOV_CAP_REG 0D80 0204h + formula
208h + formula PCIE_CORE_PFn_I_SRIOV_CTRL_STATUS_REG 0D80 0208h + formula
20Ch + formula PCIE_CORE_PFn_I_INITIAL_TOTAL_VFS_REG 0D80 020Ch + formula
210h + formula PCIE_CORE_PFn_I_FUNC_DEP_LINK_NUMVFS_REG 0D80 0210h + formula
214h + formula PCIE_CORE_PFn_I_VF_OFFSET_STRIDE_REG 0D80 0214h + formula
218h + formula PCIE_CORE_PFn_I_VF_DEVICE_ID_REG 0D80 0218h + formula
21Ch + formula PCIE_CORE_PFn_I_SUPPORTED_PAGE_SIZE_REG 0D80 021Ch + formula
220h + formula PCIE_CORE_PFn_I_SYSTEM_PAGE_SIZE_REG 0D80 0220h + formula
224h + formula PCIE_CORE_PFn_I_VF_BAR_0_REG 0D80 0224h + formula
228h + formula PCIE_CORE_PFn_I_VF_BAR_1_REG 0D80 0228h + formula
22Ch + formula PCIE_CORE_PFn_I_VF_BAR_2_REG 0D80 022Ch + formula
230h + formula PCIE_CORE_PFn_I_VF_BAR_3_REG 0D80 0230h + formula
234h + formula PCIE_CORE_PFn_I_VF_BAR_4_REG 0D80 0234h + formula
238h + formula PCIE_CORE_PFn_I_VF_BAR_5_REG 0D80 0238h + formula
23Ch + formula PCIE_CORE_PFn_I_VF_MIGRATION_STATE_ARR_OFFSET_REG 0D80 023Ch + formula
240h + formula PCIE_CORE_PFn_RSVD_090_09C 0D80 0240h + formula
300h PCIE_CORE_PF0_I_SEC_PCIE_CAP_HDR_REG 0D80 0300h
304h PCIE_CORE_PF0_I_LINK_CONTROL3_REG 0D80 0304h
308h PCIE_CORE_PF0_I_LANE_ERROR_STATUS_REG 0D80 0308h
30Ch PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG0 0D80 030Ch
310h PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG1 0D80 0310h
400h + formula PCIE_CORE_PFn_I_VSEC_HEADER_REG 0D80 0400h + formula
404h + formula PCIE_CORE_PFn_I_VENDOR_SPECIFIC_HEADER_REG 0D80 0404h + formula
408h + formula PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG 0D80 0408h + formula
40Ch + formula PCIE_CORE_PFn_I_VENDOR_SPECIFIC_DATA_REG0 0D80 040Ch + formula
440h + formula PCIE_CORE_PFn_I_PASID_HEADER_REG 0D80 0440h + formula
444h + formula PCIE_CORE_PFn_I_PASID_CAP_REG 0D80 0444h + formula
4C0h PCIE_CORE_PF0_I_VC_ENH_CAP_HEADER_REG 0D80 04C0h
4C4h PCIE_CORE_PF0_I_PORT_VC_CAP_REG_1 0D80 04C4h
4C8h PCIE_CORE_PF0_I_PORT_VC_CAP_REG_2 0D80 04C8h
4CCh PCIE_CORE_PF0_I_PORT_VC_CTRL_STS_REG 0D80 04CCh
4D0h PCIE_CORE_PF0_I_VC_RES_CAP_REG_0 0D80 04D0h
4D4h PCIE_CORE_PF0_I_VC_RES_CTRL_REG_0 0D80 04D4h
4D8h PCIE_CORE_PF0_I_VC_RES_STS_REG_0 0D80 04D8h
4DCh PCIE_CORE_PF0_I_VC_RES_CAP_REG_1 0D80 04DCh
4E0h PCIE_CORE_PF0_I_VC_RES_CTRL_REG_1 0D80 04E0h
4E4h PCIE_CORE_PF0_I_VC_RES_STS_REG_1 0D80 04E4h
4E8h PCIE_CORE_PF0_I_VC_RES_CAP_REG_2 0D80 04E8h
4ECh PCIE_CORE_PF0_I_VC_RES_CTRL_REG_2 0D80 04ECh
4F0h PCIE_CORE_PF0_I_VC_RES_STS_REG_2 0D80 04F0h
4F4h PCIE_CORE_PF0_I_VC_RES_CAP_REG_3 0D80 04F4h
4F8h PCIE_CORE_PF0_I_VC_RES_CTRL_REG_3 0D80 04F8h
4FCh PCIE_CORE_PF0_I_VC_RES_STS_REG_3 0D80 04FCh
5C0h + formula PCIE_CORE_PFn_ATS_CAP_HEADER 0D80 05C0h + formula
5C4h + formula PCIE_CORE_PFn_ATS_CAP_CONTROL 0D80 05C4h + formula
640h + formula PCIE_CORE_PFn_ATS_PR_CAP_HEADER 0D80 0640h + formula
644h + formula PCIE_CORE_PFn_ATS_PR_CONTROL_STATUS 0D80 0644h + formula
648h + formula PCIE_CORE_PFn_ATS_OUTSTANDING_PR_CAPACITY 0D80 0648h + formula
64Ch + formula PCIE_CORE_PFn_ATS_OUTSTANDING_PR_ALLOC 0D80 064Ch + formula
900h PCIE_CORE_PF0_I_L1_PM_EXT_CAP_HDR 0D80 0900h
904h PCIE_CORE_PF0_I_L1_PM_CAP 0D80 0904h
908h PCIE_CORE_PF0_I_L1_PM_CTRL_1 0D80 0908h
90Ch PCIE_CORE_PF0_I_L1_PM_CTRL_2 0D80 090Ch
910h + formula PCIE_CORE_PFn_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG 0D80 0910h + formula
914h + formula PCIE_CORE_PFn_I_DL_FEATURE_CAPABILITIES_REG 0D80 0914h + formula
918h + formula PCIE_CORE_PFn_I_DL_FEATURE_STATUS_REG 0D80 0918h + formula
920h PCIE_CORE_PF0_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG 0D80 0920h
924h PCIE_CORE_PF0_I_MARGINING_PORT_CAPABILITIES_STATUS_REG 0D80 0924h
928h PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG0 0D80 0928h
92Ch PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG1 0D80 092Ch
930h PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG2 0D80 0930h
934h PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG3 0D80 0934h
9C0h PCIE_CORE_PF0_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG 0D80 09C0h
9C4h PCIE_CORE_PF0_I_PL_16GTS_CAPABILITIES_REG 0D80 09C4h
9C8h PCIE_CORE_PF0_I_PL_16GTS_CONTROL_REG 0D80 09C8h
9CCh PCIE_CORE_PF0_I_PL_16GTS_STATUS_REG 0D80 09CCh
9D0h PCIE_CORE_PF0_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG 0D80 09D0h
9D4h PCIE_CORE_PF0_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG 0D80 09D4h
9D8h PCIE_CORE_PF0_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG 0D80 09D8h
9DCh PCIE_CORE_PF0_I_PL_16GTS_RESERVED_REG 0D80 09DCh
9E0h PCIE_CORE_PF0_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 0D80 09E0h
A20h PCIE_CORE_PF0_I_PTM_EXTENDED_CAPABILITY_HEADER_REG 0D80 0A20h
A24h PCIE_CORE_PF0_I_PTM_CAPABILITIES_REG 0D80 0A24h
A28h PCIE_CORE_PF0_I_PTM_CONTROL_REG 0D80 0A28h

3.5.1.1 PCIE_CORE_PFn_I_VENDOR_ID_DEVICE_ID Register (Offset = 0h + formula) [reset = 010017CDh]

PCIE_CORE_PFn_I_VENDOR_ID_DEVICE_ID is shown in Figure 12-1267 and described in Table 12-2472.

Return to the Summary Table.

16-bit Vendor ID register and 16-bit Device ID register.

Offset = 0h + (n * 1000h); where n = 0h to 5h

Table 12-2471 PCIE_CORE_PFn_I_VENDOR_ID_DEVICE_ID Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0000h + formula
Figure 12-1267 PCIE_CORE_PFn_I_VENDOR_ID_DEVICE_ID Register
313029282726252423222120191817161514131211109876543210
DIDVID
R/W-100hR-17CDh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2472 PCIE_CORE_PFn_I_VENDOR_ID_DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
31-16DIDR/W100hDevice ID assigned by the manufacturer of the device.
On power-up, the Controller sets it to
the value defined in the RTL file reg_defaults.h.
This field can be rewritten independently
for each Function from the local management bus.
15-0VIDR17CDhThis is the Vendor ID assigned by PCI SIG to the manufacturer of the device.
The
Vendor ID is set in the Vendor ID Register within the local management register block.

3.5.1.2 PCIE_CORE_PFn_I_COMMAND_STATUS Register (Offset = 4h + formula) [reset = 00100000h]

PCIE_CORE_PFn_I_COMMAND_STATUS is shown in Figure 12-1268 and described in Table 12-2474.

Return to the Summary Table.

16-bit Command Register and 16-bit Status Register.

Offset = 4h + (n * 1000h); where n = 0h to 5h

Table 12-2473 PCIE_CORE_PFn_I_COMMAND_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0004h + formula
Figure 12-1268 PCIE_CORE_PFn_I_COMMAND_STATUS Register
3130292827262524
DPESSERMARTASTAR6MDPE
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR-0hR/W1C-0h
2322212019181716
R5CLISR4
R-0hR-1hR-0hR-0h
15141312111098
R3IMDR2SE
R-0hR/W-0hR-0hR/W-0h
76543210
R1PERER0BEMSEISE
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2474 PCIE_CORE_PFn_I_COMMAND_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31DPER/W1C0hThis bit is set when the Controller has received a poisoned TLP.
The Parity Error Response
enable bit [bit 6] has no effect on the setting of this bit.
This field can also be cleared
from the local management bus by writing a 1 into this bit position.
30SSER/W1C0hIf the SERR enable bit is 1, this bit is set when the Controller has sent out a fatal or
non-fatal error message on the link to the Root Complex.
If the SERR enable bit is 0, this bit
remains 0.
This field can also be cleared from the local management bus by writing a 1 into
this bit position.
29RMAR/W1C0hThis bit is set when the Controller has received a completion from the link with the
Unsupported Request status.
This field can also be cleared from the local management bus by
writing a 1 into this bit position
28RTAR/W1C0hThis bit is set when the Controller has received a completion from the link with the
Completer Abort status.
This field can also be cleared from the local management bus by
writing a 1 into this bit position
27STAR/W1C0hThis bit is set when the Controller has sent a completion to the link with the Completer
Abort status.
This field can also be cleared from the local management bus by writing a 1 into
this bit position.
26-25R6R0hReserved
24MDPER/W1C0hWhen the Parity Error Response enable bit is 1, the Controller sets this bit when it detects
the following error conditions: [i] The Controller receives a poisoned completion from the link in
response to a request.
[ii] The Controller sends out a poisoned write request on the link [this may
be because an underflow occurred during the packet transfer at the host interface of the
Controller.].
This bit remains 0 when the Parity Error Response enable bit is 0.
This field can
also be cleared from the local management bus by writing a 1 into this bit position.
23-21R5R0hReserved
20CLR1hIndicates the presence of PCI Extended Capabilities registers.
This bit is hardwired
to 1.
19ISR0hThis bit is valid only when the Controller is configured to support legacy interrupts.
Indicates that the Controller has a pending interrupt, that is, the Controller has sent an Assert_INTx
message but has not transmitted a corresponding Deassert_INTx message.
18-16R4R0hReserved
15-11R3R0hReserved
10IMDR/W0hEnables or disables the transmission of INTx Assert and De-assert messages from the
Controller.
Setting this bit to 1 disables generation of INTx assert/de-assert messages in the Controller.
This field can be written from the local management bus.

9R2R0hReserved
8SER/W0hEnables the reporting of fatal and non-fatal errors detected by the Controller to the Root
Complex.
This field can be written from the local management bus.
7R1R0hReserved
6PERER/W0hWhen this bit is 1, the Controller sets the Master Data Parity Error status bit when it
detects the following error conditions: [i] The Controller receives a poisoned completion from the
link in response to a request.
[ii] The Controller sends out a poisoned write request on the link
[this may be because an underflow occurred during the packet transfer at the host interface of
the Controller.].
When this bit is 0, the Master Data Parity Error status bit is never set.
This
field can be written from the local management bus.
5-3R0R0hReserved
2BER/W0hControls the ability of a Function to issue Memory and I/O Read/Write Requests,
in the Upstream direction.
.
This field can be written from the local management bus.
Note: The Controller does not gate any requests based on this bit.
The Client Application logic must use this bit to gate requests as follows:
- When this bit is Set, the Function is allowed to issue Memory or I/O Requests on the pcie_master_AXI interface.
- When this bit is Clear, the Function must not allowed to issue any Memory or I/O Requests on the pcie_master_AXI interface.
1MSER/W0hControls a Function's response to Memory Space accesses received from PCIe Link.

The Controller internally uses this bit to respond to received Memort Requests as follows:
- When this bit is Clear, all received Memory Space accesses are handled as Unsupported Requests.

- When this bit is Set, all received Memory Space accesses are decoded and processed normally.
This field can be written from the local management bus.
0ISER/W0hControls a Function's response to IO Space accesses received from PCIe Link.

The Controller internally uses this bit to respond to received IO Requests as follows:
- When this bit is Clear, all received IO Space accesses are handled as Unsupported Requests.

- When this bit is Set, all received IO Space accesses are decoded and processed normally.
This field can be written from the local management bus.

3.5.1.3 PCIE_CORE_PFn_I_REVISION_ID_CLASS_CODE Register (Offset = 8h + formula) [reset = 0h]

PCIE_CORE_PFn_I_REVISION_ID_CLASS_CODE is shown in Figure 12-1269 and described in Table 12-2476.

Return to the Summary Table.

This register contains the Revision ID and Class Code associated with the device
incorporating the PCIe Controller.

Offset = 8h + (n * 1000h); where n = 0h to 5h

Table 12-2475 PCIE_CORE_PFn_I_REVISION_ID_CLASS_CODE Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0008h + formula
Figure 12-1269 PCIE_CORE_PFn_I_REVISION_ID_CLASS_CODE Register
313029282726252423222120191817161514131211109876543210
CCSCCPIBRID
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2476 PCIE_CORE_PFn_I_REVISION_ID_CLASS_CODE Register Field Descriptions
BitFieldTypeResetDescription
31-24CCR/W0hIdentifies the function of the device.
On power-up, the Controller sets it to the value
defined in the RTL file reg_defaults.h.
This field can be rewritten independently for each
Function from the local management bus
23-16SCCR/W0hIdentifies a sub-category within the selected function.
On power-up, the Controller sets it
to the value defined in the RTL file reg_defaults.h.
This field can be re-written
independently for each Function from the local management bus.
15-8PIBR/W0hIdentifies the register set layout of the device.
On power-up, the Controller sets it to the
value defined in the RTL file reg_defaults.h.
This field can be re-written independently for
each Function from the local management bus.
7-0RIDR/W0hAssigned by the manufacturer of the device to identify the revision number of the
device.
On power-up, the Controller sets it to the value defined in the RTL file reg_defaults.h.
This field can be re-written independently for each Function from the local management bus.

3.5.1.4 PCIE_CORE_PFn_I_BIST_HEADER_LATENCY_CACHE_LINE Register (Offset = Ch + formula) [reset = 00800000h]

PCIE_CORE_PFn_I_BIST_HEADER_LATENCY_CACHE_LINE is shown in Figure 12-1270 and described in Table 12-2478.

Return to the Summary Table.

This location contains the BIST, header-type, Latency Timer and Cache Line Size
Registers.

Offset = Ch + (n * 1000h); where n = 0h to 5h

Table 12-2477 PCIE_CORE_PFn_I_BIST_HEADER_LATENCY_CACHE_LINE Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 000Ch + formula
Figure 12-1270 PCIE_CORE_PFn_I_BIST_HEADER_LATENCY_CACHE_LINE Register
31302928272625242322212019181716
BRDTHT
R/W-0hR-1hR-0h
1514131211109876543210
LTCLS
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2478 PCIE_CORE_PFn_I_BIST_HEADER_LATENCY_CACHE_LINE Register Field Descriptions
BitFieldTypeResetDescription
31-24BRR/W0hBIST control register.It can be accessed using local management bus.
This is a sticky field.
23DTR1hIdentifies whether the device supports a single Function or multiple Functions.
This
bit is read as 0 when only Function 0 has been enabled in the Physical Function Configuration
Register [in the local management block], and as 1 when more than one Function has been
enabled.
22-16HTR0hIdentifies format of header.
This field is hardwired to 0.
15-8LTR0hThis is an unused field and is hardwired to 0.
7-0CLSR/W0hCache Line Size Register defined in PCI Specifications 3.0.
This field can be read or
written, both from the link and from the local management bus, but its value is not used.

3.5.1.5 PCIE_CORE_PFn_I_BASE_ADDR_0 Register (Offset = 10h + formula) [reset = 0h]

PCIE_CORE_PFn_I_BASE_ADDR_0 is shown in Figure 12-1271 and described in Table 12-2480.

Return to the Summary Table.

This is one of the six Base Address Registers defined by the PCI
Specifications 3.0. These registers are used to define address ranges for memory and I/O
accesses to the Endpoint device. During the initial configuration of the device, the configuration
program determines the size of
the address range defined by the BAR by writing a pattern of all 1s into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned
value. A value of 0 is returned by the Controller if BAR 0 is not configured. Otherwise, the number of
1s returned is based on the size of the BAR. BAR0 can be setup as 32-bit memory or IO BAR, or
can be paired with BAR 1 to form a 64bit memory BAR. The settings of this BAR is defined in the
BAR Configuration Register associated with this PF.
The BAR aperture can be controller in two different ways:
(i) When the Resizable BAR Capability is enabled, the aperture is
controlled by the setting of the BAR width field in Resizable BAR Control Register.
The Resizable BAR Capability is enabled by setting the Enable Resizable BAR
Capability bit (bit 31) of the associated Physical Function BAR Configuration Register 1.
(ii) When the Resizable BAR Capability is disabled for the Physical
Function, the aperture is controlled by the setting of the PF BAR
Configuration Register.

Offset = 10h + (n * 1000h); where n = 0h to 5h

Table 12-2479 PCIE_CORE_PFn_I_BASE_ADDR_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0010h + formula
Figure 12-1271 PCIE_CORE_PFn_I_BASE_ADDR_0 Register
3130292827262524
BAMRW
R/W-0h
2322212019181716
BAMRW
R/W-0h
15141312111098
BAMRWBAMR0
R/W-0hR-0h
76543210
R8P0S0R7MSI0
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2480 PCIE_CORE_PFn_I_BASE_ADDR_0 Register Field Descriptions
BitFieldTypeResetDescription
31-12BAMRWR/W0hThis field defines the base address of the memory address range.
The number of implemented
bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated
Physical Function.
11-8BAMR0R0hThis field defines the base address of the memory address range.
The number of implemented
bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated
Physical Function.
All other bits are not writeable, and are read as 0's.
7-4R8R0hThese bits are hardwired to 0
3P0R0hWhen the BAR is used to define a memory address range, this field declares whether
data from the address range is prefetchable
[0 = non-prefetchable,
1 = prefetchable].
The value read in this field is determined by the setting of BAR Configuration Registers of
the associated Physical Function
2S0R0hWhen the BAR is used to define a memory address range, this field indicates whether
the address range is
32-bit or
64-bit
[0 =
32-bit,
1 = 64 bit].
For
64-bit address ranges, the
value in BAR 1 is treated as a continuation of the base address in BAR 0.

The value read in
this field is determined by the setting of BAR Configuration Registers of the associated
Physical Function.
1R7R0hThis bit is hardwired to 0 for both memory and I/O BARs.
0MSI0R0hSpecifies whether this BAR defines a memory address range or an I/O address range
[0 =
memory,
1 = I/O].
The value read in this field is determined by the setting of BAR
Configuration Registers of the associated Physical Function

3.5.1.6 PCIE_CORE_PFn_I_BASE_ADDR_1 Register (Offset = 14h + formula) [reset = 0h]

PCIE_CORE_PFn_I_BASE_ADDR_1 is shown in Figure 12-1272 and described in Table 12-2482.

Return to the Summary Table.

This is one of the six Base Address Registers defined by the PCI
Specifications 3.0. BAR1 can be setup as 32-bit memory or IO BAR, or
can be paired with BAR 0 to form a 64bit memory BAR.
This register can be used in two distinct ways: (i) When BAR 0 defines a 64-bit memory address range,
this register is used to define the high-order bits of the base address. The number of writable bits
in this field is based on the aperture setting of the BAR. (ii) When the BAR 0 is
used to define a 32-bit memory address range or an I/O address range, this register can be used
to define a new 32-bit memory address range or an I/O address range. The individual fields in
the register have the same format as those of BAR 0 and is described below. The settings of this BAR
is defined in the BAR Configuration Register associated with this PF.
When configured as a 32-bit memory or IO BAR, the BAR aperture can be controller in two different ways:
(a) When the Resizable BAR Capability is enabled, the aperture is
controlled by the setting of the BAR width field in Resizable BAR Control Register 1.
The Resizable BAR Capability is enabled by setting the Enable Resizable BAR
Capability bit (bit 31) of the associated Physical Function BAR Configuration Register.
(b) When the Resizable BAR Capability is disabled for the Physical
Function, the aperture is controlled by the setting of the Physical Function BAR
Configuration Register.

Offset = 14h + (n * 1000h); where n = 0h to 5h

Table 12-2481 PCIE_CORE_PFn_I_BASE_ADDR_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0014h + formula
Figure 12-1272 PCIE_CORE_PFn_I_BASE_ADDR_1 Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2482 PCIE_CORE_PFn_I_BASE_ADDR_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.7 PCIE_CORE_PFn_I_BASE_ADDR_2 Register (Offset = 18h + formula) [reset = 0h]

PCIE_CORE_PFn_I_BASE_ADDR_2 is shown in Figure 12-1273 and described in Table 12-2484.

Return to the Summary Table.

This is one of the six Base Address Registers defined by the PCI
Specifications 3.0. These registers are used to define address ranges for memory and I/O
accesses to the Endpoint device. During the initial configuration of the device, the configuration
program determines the size of
the address range defined by the BAR by writing a pattern of all 1s into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned
value. A value of 0 is returned by the Controller if BAR 2 is not configured. Otherwise, the number of
1s returned is based on the size of the BAR. BAR2 can be setup as 32-bit memory or IO BAR, or
can be paired with BAR 3 to form a 64bit memory BAR. The settings of this BAR is defined in the
BAR Configuration Register associated with this PF.
The BAR aperture can be controller in two different ways:
(i) When the Resizable BAR Capability is enabled, the aperture is
controlled by the setting of the BAR width field in Resizable BAR Control Register.
The Resizable BAR Capability is enabled by setting the Enable Resizable BAR
Capability bit (bit 31) of the associated Physical Function BAR Configuration Register 1.
(ii) When the Resizable BAR Capability is disabled for the Physical
Function, the aperture is controlled by the setting of the PF BAR
Configuration Register.

Offset = 18h + (n * 1000h); where n = 0h to 5h

Table 12-2483 PCIE_CORE_PFn_I_BASE_ADDR_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0018h + formula
Figure 12-1273 PCIE_CORE_PFn_I_BASE_ADDR_2 Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2484 PCIE_CORE_PFn_I_BASE_ADDR_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.8 PCIE_CORE_PFn_I_BASE_ADDR_3 Register (Offset = 1Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_BASE_ADDR_3 is shown in Figure 12-1274 and described in Table 12-2486.

Return to the Summary Table.

This is one of the six Base Address Registers defined by the PCI
Specifications 3.0. BAR3 can be setup as 32-bit memory or IO BAR, or
can be paired with BAR 2 to form a 64bit memory BAR.
This register can be used in two distinct ways: (i) When BAR 2 defines a 64-bit memory address range,
this register is used to define the high-order bits of the base address. The number of writable bits
in this field is based on the aperture setting of the BAR. (ii) When the BAR 2 is
used to define a 32-bit memory address range or an I/O address range, this register can be used
to define a new 32-bit memory address range or an I/O address range. The individual fields in
the register have the same format as those of BAR 2 and is described below. The settings of this BAR
is defined in the BAR Configuration Register associated with this PF.
When configured as a 32-bit memory or IO BAR, the BAR aperture can be controller in two different ways:
(a) When the Resizable BAR Capability is enabled, the aperture is
controlled by the setting of the BAR width field in Resizable BAR Control Register 3.
The Resizable BAR Capability is enabled by setting the Enable Resizable BAR
Capability bit (bit 31) of the associated Physical Function BAR Configuration Register.
(b) When the Resizable BAR Capability is disabled for the Physical
Function, the aperture is controlled by the setting of the Physical Function BAR
Configuration Register.

Offset = 1Ch + (n * 1000h); where n = 0h to 5h

Table 12-2485 PCIE_CORE_PFn_I_BASE_ADDR_3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 001Ch + formula
Figure 12-1274 PCIE_CORE_PFn_I_BASE_ADDR_3 Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2486 PCIE_CORE_PFn_I_BASE_ADDR_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.9 PCIE_CORE_PFn_I_BASE_ADDR_4 Register (Offset = 20h + formula) [reset = 0h]

PCIE_CORE_PFn_I_BASE_ADDR_4 is shown in Figure 12-1275 and described in Table 12-2488.

Return to the Summary Table.

This is one of the six Base Address Registers defined by the PCI
Specifications 3.0. These registers are used to define address ranges for memory and I/O
accesses to the Endpoint device. During the initial configuration of the device, the configuration
program determines the size of
the address range defined by the BAR by writing a pattern of all 1s into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned
value. A value of 0 is returned by the Controller if BAR 4 is not configured. Otherwise, the number of
1s returned is based on the size of the BAR. BAR4 can be setup as 32-bit memory or IO BAR, or
can be paired with BAR 5 to form a 64bit memory BAR. The settings of this BAR is defined in the
BAR Configuration Register associated with this PF.
The BAR aperture can be controller in two different ways:
(i) When the Resizable BAR Capability is enabled, the aperture is
controlled by the setting of the BAR width field in Resizable BAR Control Register.
The Resizable BAR Capability is enabled by setting the Enable Resizable BAR
Capability bit (bit 31) of the associated Physical Function BAR Configuration Register 1.
(ii) When the Resizable BAR Capability is disabled for the Physical
Function, the aperture is controlled by the setting of the PF BAR
Configuration Register.

Offset = 20h + (n * 1000h); where n = 0h to 5h

Table 12-2487 PCIE_CORE_PFn_I_BASE_ADDR_4 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0020h + formula
Figure 12-1275 PCIE_CORE_PFn_I_BASE_ADDR_4 Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2488 PCIE_CORE_PFn_I_BASE_ADDR_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.10 PCIE_CORE_PFn_I_BASE_ADDR_5 Register (Offset = 24h + formula) [reset = 0h]

PCIE_CORE_PFn_I_BASE_ADDR_5 is shown in Figure 12-1276 and described in Table 12-2490.

Return to the Summary Table.

This is one of the six Base Address Registers defined by the PCI
Specifications 3.0. BAR5 can be setup as 32-bit memory or IO BAR, or
can be paired with BAR 4 to form a 64bit memory BAR.
This register can be used in two distinct ways: (i) When BAR 4 defines a 64-bit memory address range,
this register is used to define the high-order bits of the base address. The number of writable bits
in this field is based on the aperture setting of the BAR. (ii) When the BAR 4 is
used to define a 32-bit memory address range or an I/O address range, this register can be used
to define a new 32-bit memory address range or an I/O address range. The individual fields in
the register have the same format as those of BAR 4 and is described below. The settings of this BAR
is defined in the BAR Configuration Register associated with this PF.
When configured as a 32-bit memory or IO BAR, the BAR aperture can be controller in two different ways:
(a) When the Resizable BAR Capability is enabled, the aperture is
controlled by the setting of the BAR width field in Resizable BAR Control Register 5.
The Resizable BAR Capability is enabled by setting the Enable Resizable BAR
Capability bit (bit 31) of the associated Physical Function BAR Configuration Register.
(b) When the Resizable BAR Capability is disabled for the Physical
Function, the aperture is controlled by the setting of the Physical Function BAR
Configuration Register.

Offset = 24h + (n * 1000h); where n = 0h to 5h

Table 12-2489 PCIE_CORE_PFn_I_BASE_ADDR_5 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0024h + formula
Figure 12-1276 PCIE_CORE_PFn_I_BASE_ADDR_5 Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2490 PCIE_CORE_PFn_I_BASE_ADDR_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.11 PCIE_CORE_PFn_RSVD_0A Register (Offset = 28h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_0A is shown in Figure 12-1277 and described in Table 12-2492.

Return to the Summary Table.

Reserved

Offset = 28h + (n * 1000h); where n = 0h to 5h

Table 12-2491 PCIE_CORE_PFn_RSVD_0A Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0028h + formula
Figure 12-1277 PCIE_CORE_PFn_RSVD_0A Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2492 PCIE_CORE_PFn_RSVD_0A Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.12 PCIE_CORE_PFn_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I Register (Offset = 2Ch + formula) [reset = 17CDh]

PCIE_CORE_PFn_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I is shown in Figure 12-1278 and described in Table 12-2494.

Return to the Summary Table.

This register contains the Subsystem Vendor ID and Subsystem ID associated with the
device incorporating the PCIe Controller.

Offset = 2Ch + (n * 1000h); where n = 0h to 5h

Table 12-2493 PCIE_CORE_PFn_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 002Ch + formula
Figure 12-1278 PCIE_CORE_PFn_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I Register
313029282726252423222120191817161514131211109876543210
SIDSVID
R/W-0hR-17CDh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2494 PCIE_CORE_PFn_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I Register Field Descriptions
BitFieldTypeResetDescription
31-16SIDR/W0hSpecifies the Subsystem ID assigned by the manufacturer of the device.
On power-up,
the Controller sets it to the value defined in the RTL file reg_defaults.h.
This field can be
re-written independently for each Function from the local management bus.
15-0SVIDR17CDhSpecifies the Subsystem Vendor ID assigned by the PCI SIG to the manufacturer of the
device.
Its value comes fom the Subsystem Vendor ID Register in the local management register
block.

3.5.1.13 PCIE_CORE_PFn_RSVD_0C Register (Offset = 30h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_0C is shown in Figure 12-1279 and described in Table 12-2496.

Return to the Summary Table.

Reserved

Offset = 30h + (n * 1000h); where n = 0h to 5h

Table 12-2495 PCIE_CORE_PFn_RSVD_0C Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0030h + formula
Figure 12-1279 PCIE_CORE_PFn_RSVD_0C Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2496 PCIE_CORE_PFn_RSVD_0C Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.14 PCIE_CORE_PFn_I_CAPABILITIES_POINTER Register (Offset = 34h + formula) [reset = 80h]

PCIE_CORE_PFn_I_CAPABILITIES_POINTER is shown in Figure 12-1280 and described in Table 12-2498.

Return to the Summary Table.

This location contains the pointer to the first PCI Capabilities Structure. Its default
value points to the Power Management Capability Structure (register number 0x80 hex).

Offset = 34h + (n * 1000h); where n = 0h to 5h

Table 12-2497 PCIE_CORE_PFn_I_CAPABILITIES_POINTER Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0034h + formula
Figure 12-1280 PCIE_CORE_PFn_I_CAPABILITIES_POINTER Register
313029282726252423222120191817161514131211109876543210
R15CP
R-0hR/W-80h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2498 PCIE_CORE_PFn_I_CAPABILITIES_POINTER Register Field Descriptions
BitFieldTypeResetDescription
31-8R15R0hReserved
7-0CPR/W80hContains pointer to the first PCI Capability Structure.
This field is set by default
to the value defined in the RTL file reg_defaults.h.
It can be re-written independently for
every Function from the local management bus.

3.5.1.15 PCIE_CORE_PFn_RSVD_0E Register (Offset = 38h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_0E is shown in Figure 12-1281 and described in Table 12-2500.

Return to the Summary Table.

Reserved

Offset = 38h + (n * 1000h); where n = 0h to 5h

Table 12-2499 PCIE_CORE_PFn_RSVD_0E Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0038h + formula
Figure 12-1281 PCIE_CORE_PFn_RSVD_0E Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2500 PCIE_CORE_PFn_RSVD_0E Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.16 PCIE_CORE_PFn_I_INTRPT_LINE_INTRPT_PIN Register (Offset = 3Ch + formula) [reset = 1FFh]

PCIE_CORE_PFn_I_INTRPT_LINE_INTRPT_PIN is shown in Figure 12-1282 and described in Table 12-2502.

Return to the Summary Table.

This location contains the PCI 3.0 Interrupt Line and Interrupt Pin Registers. These
registers are used only when the Controller is configured to support PCI legacy interrupts. If the
legacy interrupt mode is configured, the Controller receives interrupt indications from the client
logic on its INTA_IN, INTB_IN, INTC_IN and INTD_IN inputs, and sends out Assert_INTx or
Deassert_INTx messages on the link in response to their activation or deactivation,
respectively. The Interrupt Pin Register defines which of the four inputs is connected to the
Function corresponding to this register set. The Interrupt Line register defines the input of
the interrupt controller (IRQ0 - IRQ15) in the Root Complex that is activated by each
Assert_INTx message.

Offset = 3Ch + (n * 1000h); where n = 0h to 5h

Table 12-2501 PCIE_CORE_PFn_I_INTRPT_LINE_INTRPT_PIN Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 003Ch + formula
Figure 12-1282 PCIE_CORE_PFn_I_INTRPT_LINE_INTRPT_PIN Register
313029282726252423222120191817161514131211109876543210
R16IPRILR
R-0hR/W-1hR/W-FFh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2502 PCIE_CORE_PFn_I_INTRPT_LINE_INTRPT_PIN Register Field Descriptions
BitFieldTypeResetDescription
31-11R16R0hReserved
10-8IPRR/W1hIdentifies the interrupt input [A, B, C, D] to which this Functions interrupt output
is connected to
[01 = INTA,
02 = INTB,
03 = INTC,
04 = INTD].
The assignment of interrupt
inputs to Functions is fixed when the Controller is configured.
This field can be re-written
independently for each Function from the local management bus.
Please see the define macros den_db_Fx_INTR_PIN values [where x is the function number] for
default values of each function in the reg_defaults.v files.
7-0ILRR/WFFhIdentifies the IRQx input of the interrupt controller at the Root Complex that is
activated by this Functions interrupt
[00 = IRQ0, ...
, 0F = IRQ15, FF = unknown or not
connected].
This field is writable from the local management bus.
Please see the define macros den_db_Fx_INTR_LINE values [where x is the function number] for
default values of each function in the reg_defaults.v files.

3.5.1.17 PCIE_CORE_PFn_RSVD_010_01F Register (Offset = 40h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_010_01F is shown in Figure 12-1283 and described in Table 12-2504.

Return to the Summary Table.

Reserved

Offset = 40h + (n * 1000h); where n = 0h to 5h

Table 12-2503 PCIE_CORE_PFn_RSVD_010_01F Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0040h + formula
Figure 12-1283 PCIE_CORE_PFn_RSVD_010_01F Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2504 PCIE_CORE_PFn_RSVD_010_01F Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.18 PCIE_CORE_PFn_I_PWR_MGMT_CAP Register (Offset = 80h + formula) [reset = 5A039001h]

PCIE_CORE_PFn_I_PWR_MGMT_CAP is shown in Figure 12-1284 and described in Table 12-2506.

Return to the Summary Table.

This location contains the Power Management Capabilities Register, its Capability ID,
and a pointer to the next capability. This version of the Controller supports the PCI power states D0
,D1 and D3.

Offset = 80h + (n * 1000h); where n = 0h to 5h

Table 12-2505 PCIE_CORE_PFn_I_PWR_MGMT_CAP Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0080h + formula
Figure 12-1284 PCIE_CORE_PFn_I_PWR_MGMT_CAP Register
3130292827262524
PSDCSPSDHSPSD2SPSD1SPSD0SD2SD1SMCRAPS
R-0hR/W-1hR-0hR/W-1hR/W-1hR-0hR/W-1hR-0h
2322212019181716
MCRAPSDSIR0PCVID
R-0hR-0hR-0hR-0hR/W-3h
15141312111098
CP
R/W-90h
76543210
CID
R/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2506 PCIE_CORE_PFn_I_PWR_MGMT_CAP Register Field Descriptions
BitFieldTypeResetDescription
31PSDCSR0hIndicates whether the Function is capable of sending PME messages when in the D3cold
state.
Because the device does not have aux power, this bit is hardwired to 0.
30PSDHSR/W1hIndicates whether the Function is capable of sending PME messages when in the D3hot
state.
This bit is set to 1 by default, but can be modified from the local management bus by
writing into Function 0.
All other Functions assume the value set in Function 0s Power
Management Capabilities Register.
29PSD2SR0hIndicates whether the Function is capable of sending PME messages when in the D2
state.
This bit is hardwired to 0 because D2 state is not supported.
28PSD1SR/W1hIndicates whether the Function is capable of sending PME messages when in the D1
state.
This bit can be modified from the local management bus by
writing into Function 0.
All other Functions assume the value set in Function 0s Power
Management Capabilities Register.
27PSD0SR/W1hIndicates whether the Function is capable of sending PME messages when in the D0
state.
This bit is set to 1 by default, but can be modified from the local management bus by
writing into Function 0.
All other Functions assume the value set in Function 0s Power
Management Capabilities Register.
26D2SR0hSet if the Function supports the D2 power state.
Currently hardwired to 0.
25D1SR/W1hSet if the Function supports the D1 power state.
This bit can be modified from
the local management bus by writing into Function 0.
All other Functions
assume the value set in Function 0s Power Management Capabilities Register.
24-22MCRAPSR0hSpecifies the maximum current drawn by the device from the aux power source in the
D3cold state.
This field is not implemented in devices not supporting PME notification when in
the D3cold state, and is therefore hardwired to 0.
21DSIR0hThis bit, when set, indicates that the device requires additional configuration steps
beyond setting up its PCI configuration space, to bring it to the D0 active state from the
D0 uninitialized state.
This bit is hardwired to 0.
20R0R0hReserved
19PCR0hNot applicable to PCI Express.
This bit is hardwired to 0.
18-16VIDR/W3hIndicates the version of the PCI Bus Power Management Specifications that the Function
implements.
This field is set by default to 011 [Version 1.2].
It can be re-written
independently for each Function from the local management bus.
15-8CPR/W90hContains pointer to the next PCI Capability Structure.
The Controller sets it to the value
defined in the RTL file reg_defaults.h.
This field can be re-written independently for each Function
from the local management bus.
7-0CIDR/W1hIdentifies that the capability structure is for Power Management.
This field is set by
default to 01 hex.
It can be re-written independently for each Function from the local
management bus.

3.5.1.19 PCIE_CORE_PFn_I_PWR_MGMT_CTRL_STAT_REP Register (Offset = 84h + formula) [reset = 8h]

PCIE_CORE_PFn_I_PWR_MGMT_CTRL_STAT_REP is shown in Figure 12-1285 and described in Table 12-2508.

Return to the Summary Table.

This location contains the Power Management Control/Status and Data Registers.

Offset = 84h + (n * 1000h); where n = 0h to 5h

Table 12-2507 PCIE_CORE_PFn_I_PWR_MGMT_CTRL_STAT_REP Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0084h + formula
Figure 12-1285 PCIE_CORE_PFn_I_PWR_MGMT_CTRL_STAT_REP Register
3130292827262524
DR
R-0h
2322212019181716
R1
R-0h
15141312111098
PMESR2PE
R/W-0hR-0hR/W-0h
76543210
R3NSRR4PS
R-0hR/W-1hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2508 PCIE_CORE_PFn_I_PWR_MGMT_CTRL_STAT_REP Register Field Descriptions
BitFieldTypeResetDescription
31-24DRR0hThis optional register is not implemented in the PCIe Controller.
This field is
hardwired to 0.
23-16R1R0hReserved
15PMESR/W0hWhen PME notification is enabled, writing a 1 into this bit position from the local
management bus sets this bit and causes the Controller to send a PME message from the associated
Function.
When the Root Complex processes this message, it will turn off this bit by writing a
1 into this bit position through a Config Write.
This bit can be set or cleared from the local
management bus, by writing a 1 or 0, respectively.
It can only be cleared from the
configuration path [by writing a 1].
This is a sticky field.
14-9R2R0hReserved
8PER/W0hSetting this bit enables the notification of PME events from the associated Function.
This bit can be set also by writing into this register from the local management bus.
This is a sticky field.
7-4R3R0hReserved
3NSRR/W1hWhen this bit is set to 1, the Function will maintain all its state in the PM state
D3hot.
The software is not required to re-initialize the Function registers on the transition
back to D0.
This bit is set to 1 by default, but can be modified independently for each PF from
the local management bus.
2R4R0hReserved
1-0PSR/W0hIndicates the power state this Function is currently in.
This field can be read by the
software to monitor the current power state, or can be written to cause a transition to a new
state.
The valid settings are 00 [state D0], 01 [state D1] and 11 [state D3hot].
The software
should not write any other value into this field.
This field can also be written from the
local management bus independently for each Function.

3.5.1.20 PCIE_CORE_PFn_RSVD_022_023 Register (Offset = 88h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_022_023 is shown in Figure 12-1286 and described in Table 12-2510.

Return to the Summary Table.

Reserved

Offset = 88h + (n * 1000h); where n = 0h to 5h

Table 12-2509 PCIE_CORE_PFn_RSVD_022_023 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0088h + formula
Figure 12-1286 PCIE_CORE_PFn_RSVD_022_023 Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2510 PCIE_CORE_PFn_RSVD_022_023 Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.21 PCIE_CORE_PFn_I_MSI_CTRL_REG Register (Offset = 90h + formula) [reset = 0180B005h]

PCIE_CORE_PFn_I_MSI_CTRL_REG is shown in Figure 12-1287 and described in Table 12-2512.

Return to the Summary Table.

This register is used only when the Controller is configured to support Message Signaled
Interrupts (MSIs). In addition to the MSI control bits, this location also contains the
Capability ID for MSI and the pointer to the next PCI Capability Structure.

Offset = 90h + (n * 1000h); where n = 0h to 5h

Table 12-2511 PCIE_CORE_PFn_I_MSI_CTRL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0090h + formula
Figure 12-1287 PCIE_CORE_PFn_I_MSI_CTRL_REG Register
3130292827262524
R0MC
R-0hR/W-1h
2322212019181716
BAC64MMEMMCME
R/W-1hR/W-0hR/W-0hR/W-0h
15141312111098
CP1
R/W-B0h
76543210
CID1
R-5h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2512 PCIE_CORE_PFn_I_MSI_CTRL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-25R0R0hReserved
24MCR/W1hcan be modified using localmanagement interface
23BAC64R/W1hSet to 1 to indicate that the device is capable of generating
64-bit addresses for MSI
messages.Can be modified using local management interface
22-20MMER/W0hEncodes the number of distinct messages that the Controller is programmed to generate for
this Function
[000 = 1,
001 = 2,
010 = 4,
011 = 8,
100 = 16,
101 = 32].
This setting must be
based on the number of interrupt inputs of the Controller that are actually used by this Function.
This field can be written from the local management bus.
19-17MMCR/W0hEncodes the number of distinct messages that the Controller is capable of generating for
this Function
[000 = 1,
001 = 2,
010 = 4,
011 = 8,
100 = 16,
101 = 32].
Thus, this field
defines the number of the interrupt vectors for this Function.
The Controller allows up to 32
distinct messages, but the setting of this field must be based on the number of interrupt
inputs of the Controller that are actually used by the client.
For example, if the client logic uses
8 of the 32 distinct MSI interrupt inputs of the Controller for this Function, then the value of
this field must be set to 011.
This field can be written from the local management bus.
Please see the define den_db_Fx_MSI_MULTIPLE_MSG_CAPABLE values [where x is the function number]
for default values of each function in the reg_defaults.v files.
16MER/W0hSet by the configuration program to enable the MSI feature.
This field can also be
written from the local management bus.
15-8CP1R/WB0hPointer to the next PCI Capability Structure.
This can be modified from the local management
bus.
This field
can be written from the local management bus.
7-0CID1R5hSpecifies that the capability structure is for MSI.
Hardwired to 05 hex.

3.5.1.22 PCIE_CORE_PFn_I_MSI_MSG_LOW_ADDR Register (Offset = 94h + formula) [reset = 0h]

PCIE_CORE_PFn_I_MSI_MSG_LOW_ADDR is shown in Figure 12-1288 and described in Table 12-2514.

Return to the Summary Table.

This register contains the first 32 bits of the address to be used in the MSI messages
generated by the Controller for this Function. This address is taken as a 32-bit address if the value
programmed in the MSI Message High Address Register is 0. Otherwise, this address is taken as
the least significant 32 bits of the 64-bit address sent in MSI messages.

Offset = 94h + (n * 1000h); where n = 0h to 5h

Table 12-2513 PCIE_CORE_PFn_I_MSI_MSG_LOW_ADDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0094h + formula
Figure 12-1288 PCIE_CORE_PFn_I_MSI_MSG_LOW_ADDR Register
313029282726252423222120191817161514131211109876543210
MALR1
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2514 PCIE_CORE_PFn_I_MSI_MSG_LOW_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-2MALR/W0hLower bits of the address to be used in MSI messages.
This field can also be written
from the local management bus.
1-0R1R0hThe two lower bits of the address are hardwired to 0 to align the address on a
double-word boundary.

3.5.1.23 PCIE_CORE_PFn_I_MSI_MSG_HI_ADDR Register (Offset = 98h + formula) [reset = 0h]

PCIE_CORE_PFn_I_MSI_MSG_HI_ADDR is shown in Figure 12-1289 and described in Table 12-2516.

Return to the Summary Table.

This register contains the most significant 32 bits of the 64-bit address sent by the
Controller in MSI messages. A value of all zeroes in this register is taken to mean that the Controller
should use 32-bit addresses in the messages.

Offset = 98h + (n * 1000h); where n = 0h to 5h

Table 12-2515 PCIE_CORE_PFn_I_MSI_MSG_HI_ADDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0098h + formula
Figure 12-1289 PCIE_CORE_PFn_I_MSI_MSG_HI_ADDR Register
313029282726252423222120191817161514131211109876543210
MAH
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2516 PCIE_CORE_PFn_I_MSI_MSG_HI_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0MAHR/W0hContains bits 63:32 of the 64-bit address to be used in MSI Messages.
A value of 0
specifies that 32-bit addresses are to be used in the messages.
This field can also be written
from the local management bus.

3.5.1.24 PCIE_CORE_PFn_I_MSI_MSG_DATA Register (Offset = 9Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_MSI_MSG_DATA is shown in Figure 12-1290 and described in Table 12-2518.

Return to the Summary Table.

This register contains the write data to be used in the MSI messages to be generated for
the associated PCI Function. When the number of distinct messages programmed in the MSI Control
Register is 1, the 32-bit value from this register is used as the data value in the MSI packets
generated by the Controller for this Function. If the number of distinct messages is more than 1, the
least significant bits of the programmed value are replaced with the encoded interrupt vector
[31:0] of the specific message to generate the write data value for the message.

Offset = 9Ch + (n * 1000h); where n = 0h to 5h

Table 12-2517 PCIE_CORE_PFn_I_MSI_MSG_DATA Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 009Ch + formula
Figure 12-1290 PCIE_CORE_PFn_I_MSI_MSG_DATA Register
313029282726252423222120191817161514131211109876543210
R2MD
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2518 PCIE_CORE_PFn_I_MSI_MSG_DATA Register Field Descriptions
BitFieldTypeResetDescription
31-16R2R0hHardwired to 0
15-0MDR/W0hMessage data to be used for this Function.
This field can also be written from the
local management bus.

3.5.1.25 PCIE_CORE_PFn_I_MSI_MASK Register (Offset = A0h + formula) [reset = 0h]

PCIE_CORE_PFn_I_MSI_MASK is shown in Figure 12-1291 and described in Table 12-2520.

Return to the Summary Table.

This register contains the MSI mask bits, one for each of the interrupt levels.

Offset = A0h + (n * 1000h); where n = 0h to 5h

Table 12-2519 PCIE_CORE_PFn_I_MSI_MASK Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00A0h + formula
Figure 12-1291 PCIE_CORE_PFn_I_MSI_MASK Register
31302928272625242322212019181716
R0
R-0h
1514131211109876543210
R0MM
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2520 PCIE_CORE_PFn_I_MSI_MASK Register Field Descriptions
BitFieldTypeResetDescription
31-1R0R0hPlease note that if the Multiple Message Capable field is changed from the local management APBbus, then
the width of this field also changes correspondingly
0MMR/W0hMask bits for MSI interrupts.

The Multiple Message Capable field of the MSI Control Register specifies the number of
distinct interrupts for the Function, which determines the number of valid mask bits.
Please note that if the Multiple Message Capable field is changed from the local management APBbus, then
the width of the MSI Mask field also changes correspondingly

3.5.1.26 PCIE_CORE_PFn_I_MSI_PENDING_BITS Register (Offset = A4h + formula) [reset = 0h]

PCIE_CORE_PFn_I_MSI_PENDING_BITS is shown in Figure 12-1292 and described in Table 12-2522.

Return to the Summary Table.

This register contains the MSI pending interrupt bits, one for each of the interrupt
levels.

Offset = A4h + (n * 1000h); where n = 0h to 5h

Table 12-2521 PCIE_CORE_PFn_I_MSI_PENDING_BITS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00A4h + formula
Figure 12-1292 PCIE_CORE_PFn_I_MSI_PENDING_BITS Register
31302928272625242322212019181716
R0
R-0h
1514131211109876543210
R0MP
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2522 PCIE_CORE_PFn_I_MSI_PENDING_BITS Register Field Descriptions
BitFieldTypeResetDescription
31-1R0R0hPlease note that if the Multiple Message Capable field is changed from the local management APBbus, then
the width of this field also changes correspondingly
0MPR/W0hPending bits for MSI interrupts.



This field can be written from either the APB interface or the MSI_PENDING_STATUS_IN inputs of
the Controller depending on the MSI Pending Status In Mode select Bit in the Local Management
space.


The Multiple Message Capable field of the MSI Control Register specifies the number of
distinct interrupts for the Function, which determines the number of valid pending bits.
Please note that if the Multiple Message Capable field is changed from the local management APBbus, then
the width of the MSI Pending Bits field also changes correspondingly

3.5.1.27 PCIE_CORE_PFn_RSVD_02A_02B Register (Offset = A8h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_02A_02B is shown in Figure 12-1293 and described in Table 12-2524.

Return to the Summary Table.

Reserved

Offset = A8h + (n * 1000h); where n = 0h to 5h

Table 12-2523 PCIE_CORE_PFn_RSVD_02A_02B Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00A8h + formula
Figure 12-1293 PCIE_CORE_PFn_RSVD_02A_02B Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2524 PCIE_CORE_PFn_RSVD_02A_02B Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.28 PCIE_CORE_PFn_I_MSIX_CTRL Register (Offset = B0h + formula) [reset = C011h]

PCIE_CORE_PFn_I_MSIX_CTRL is shown in Figure 12-1294 and described in Table 12-2526.

Return to the Summary Table.

This register contains the MSI-X configuration bits, the Capability ID for MSI-X and the
pointer to the next PCI Capability Structure.

Offset = B0h + (n * 1000h); where n = 0h to 5h

Table 12-2525 PCIE_CORE_PFn_I_MSIX_CTRL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00B0h + formula
Figure 12-1294 PCIE_CORE_PFn_I_MSIX_CTRL Register
3130292827262524
MSIXEFMR0MSIXTS
R/W-0hR/W-0hR-0hR/W-0h
2322212019181716
MSIXTS
R/W-0h
15141312111098
CP
R/W-C0h
76543210
CID
R/W-11h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2526 PCIE_CORE_PFn_I_MSIX_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31MSIXER/W0hSet by the configuration program to enable the MSI-X feature.
This field can also be
written from the local management bus.
30FMR/W0hThis bit serves as a global mask to all the interrupt conditions associated with this
Function.
When this bit is set, the Controller will not send out MSI-X messages from this Function.
This field can also be written from the local management bus.
29-27R0R0hReserved
26-16MSIXTSR/W0hSpecifies the size of the MSI-X Table, that is, the number of interrupt vectors
defined for the Function.
The programmed value is 1 minus the size of the table [that is, this
field is set to 0 if the table size is 1.].
It can be
re-written independently for each Function from the local management bus.
Please see the define den_db_Fx_MSIX_TABLE_SIZE values [where x is the function number]
for default values of each function in the reg_defaults.v files.
15-8CPR/WC0hContains pointer to the next PCI Capability Structure.
This is set to point to the PCI
Express Capability Structure at 30 hex.
This can be rewritten independently for each Function
from the local management bus.
7-0CIDR/W11hIdentifies that the capability structure is for MSI-X.
This field is set by default to
11 hex.
It can be rewritten independently for each Function from the local management bus.

3.5.1.29 PCIE_CORE_PFn_I_MSIX_TBL_OFFSET Register (Offset = B4h + formula) [reset = 0h]

PCIE_CORE_PFn_I_MSIX_TBL_OFFSET is shown in Figure 12-1295 and described in Table 12-2528.

Return to the Summary Table.

This register is used to specify the location of the MSI-X Table in memory. All the 32
bits of this register can be re-written independently for each Function from the local
management bus.

Offset = B4h + (n * 1000h); where n = 0h to 5h

Table 12-2527 PCIE_CORE_PFn_I_MSIX_TBL_OFFSET Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00B4h + formula
Figure 12-1295 PCIE_CORE_PFn_I_MSIX_TBL_OFFSET Register
31302928272625242322212019181716
TO
R/W-0h
1514131211109876543210
TOBARI
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2528 PCIE_CORE_PFn_I_MSIX_TBL_OFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-3TOR/W0hOffset of the memory address where the MSI-X Table is located, relative to the
selected BAR.
The three least significant bits of the address are omitted, as the addresses
are QWORD aligned.
Please see the define den_db_Fx_MSIX_TABLE_OFFSET values [where x is the function number]
for default values of each function in the reg_defaults.v files.
2-0BARIR/W0hIdentifies the BAR corresponding to the memory address range where the MSI-X Table is
located
[000 = BAR 0,
001 = BAR 1, ...
,
101 = BAR 5].
Please see the define den_db_Fx_MSIX_TABLE_BIR values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.30 PCIE_CORE_PFn_I_MSIX_PENDING_INTRPT Register (Offset = B8h + formula) [reset = 8h]

PCIE_CORE_PFn_I_MSIX_PENDING_INTRPT is shown in Figure 12-1296 and described in Table 12-2530.

Return to the Summary Table.

This register is used to specify the location of the MSI-X Pending Bit Array (PBA). The
PBA is a structure in memory containing the pending interrupt bits. All the 32 bits of this
register can be rewritten independently for each Function from the local management bus.

Offset = B8h + (n * 1000h); where n = 0h to 5h

Table 12-2529 PCIE_CORE_PFn_I_MSIX_PENDING_INTRPT Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00B8h + formula
Figure 12-1296 PCIE_CORE_PFn_I_MSIX_PENDING_INTRPT Register
31302928272625242322212019181716
PBAO
R/W-1h
1514131211109876543210
PBAOBARI1
R/W-1hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2530 PCIE_CORE_PFn_I_MSIX_PENDING_INTRPT Register Field Descriptions
BitFieldTypeResetDescription
31-3PBAOR/W1hOffset of the memory address where the PBA is located, relative to the selected BAR.
The three least significant bits of the address are omitted, as the addresses are QWORD
aligned.
Please see the define den_db_Fx_MSIX_PBA_OFFSET values [where x is the function number]
for default values of each function in the reg_defaults.v files.
2-0BARI1R/W0hIdentifies the BAR corresponding to the memory address range where the PBA Structure
is located
[000 = BAR 0,
001 = BAR 1, ...
,
101 = BAR 5].
The value programmed must be the
same as the BAR Indicator configured in the MSI-X Table Offset Register.Identifies the BAR
corresponding to the memory address range where the PBA Structure is located
[000 = BAR 0, 001
= BAR 1, ...
,
101 = BAR 5].
The value programmed must be the same as the BAR Indicator
configured in the MSI-X Table Offset Register.
Please see the define den_db_Fx_MSIX_PBA_BIR values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.31 PCIE_CORE_PFn_RSVD_02F Register (Offset = BCh + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_02F is shown in Figure 12-1297 and described in Table 12-2532.

Return to the Summary Table.

Reserved

Offset = BCh + (n * 1000h); where n = 0h to 5h

Table 12-2531 PCIE_CORE_PFn_RSVD_02F Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00BCh + formula
Figure 12-1297 PCIE_CORE_PFn_RSVD_02F Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2532 PCIE_CORE_PFn_RSVD_02F Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.32 PCIE_CORE_PFn_I_PCIE_CAP_LIST Register (Offset = C0h + formula) [reset = 00020010h]

PCIE_CORE_PFn_I_PCIE_CAP_LIST is shown in Figure 12-1298 and described in Table 12-2534.

Return to the Summary Table.

This location identifies the PCI Express device type and its capabilities. It also
contains the Capability ID for the PCI Express Structure and the pointer to the next capability
structure.

Offset = C0h + (n * 1000h); where n = 0h to 5h

Table 12-2533 PCIE_CORE_PFn_I_PCIE_CAP_LIST Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00C0h + formula
Figure 12-1298 PCIE_CORE_PFn_I_PCIE_CAP_LIST Register
31302928272625242322212019181716
R0TRSIMNSSDTPCV
R-0hR-0hR-0hR-0hR-0hR/W-2h
1514131211109876543210
NCPCID
R-0hR-10h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2534 PCIE_CORE_PFn_I_PCIE_CAP_LIST Register Field Descriptions
BitFieldTypeResetDescription
31R0R0hReserved
30TRSR0hWhen set to 1, this bit indicates that the device supports routing of Trusted
Configuration Requests.
Not valid for Endpoints.
Hardwired to 0.
29-25IMNR0hIdentifies the MSI or MSI-X interrupt vector for the interrupt message generated
corresponding to the status bits in the Slot Status Register, Root Status Register, or this
capability structure.
This field must be defined based on the chosen interrupt mode - MSI or
MSI-X.
This field is hardwired to 0.
24SSR0hSet to 1 when the link connected to a slot.
Hardwired to 0.
23-20DTR0hIndicates the type of device implementing this Function.
This field is hardwired to 0
in the EP mode.
19-16PCVR/W2hIdentifies the version number of the capability structure.

This field is set to 2 by default to indicate that the Controller is compatible to PCI Express Base Specification Revision 3.0.
This field can be modified through local management interface.
15-8NCPR0hPoints to the next PCI capability structure.
Set to 0 because this is the last
capability structure.
7-0CIDR10hSpecifies Capability ID assigned by PCI SIG for this structure.
This field is
hardwired to 10 hex.

3.5.1.33 PCIE_CORE_PFn_I_PCIE_DEV_CAP Register (Offset = C4h + formula) [reset = 10008101h]

PCIE_CORE_PFn_I_PCIE_DEV_CAP is shown in Figure 12-1299 and described in Table 12-2536.

Return to the Summary Table.

This register advertises the capabilities of the PCI Express device encompassing this
Function.

Offset = C4h + (n * 1000h); where n = 0h to 5h

Table 12-2535 PCIE_CORE_PFn_I_PCIE_DEV_CAP Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00C4h + formula
Figure 12-1299 PCIE_CORE_PFn_I_PCIE_DEV_CAP Register
3130292827262524
R3FCCPLSCSPLV
R-0hR/W-1hR/W-0hR/W-0h
2322212019181716
CSPLVR2
R/W-0hR-0h
15141312111098
RBERR1AL1SLAL0SL
R/W-1hR-0hR/W-0hR/W-4h
76543210
AL0SLETFSPFSMPS
R/W-4hR-0hR-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2536 PCIE_CORE_PFn_I_PCIE_DEV_CAP Register Field Descriptions
BitFieldTypeResetDescription
31-29R3R0hReserved
28FCR/W1hSet when device has Function-Level Reset capability.
It is set by default to 1.
It can
be re-written independently for each Function from the local management bus.
27-26CPLSR/W0hSpecifies the scale used by Slot Power Limit Value.
It is set by default to the value
define in reg_defaults.h.
It can be re-written independently for each Function from the local
management bus.
25-18CSPLVR/W0hSpecifies upper limit on power supplied by slot.
It is set by default to the value
define in reg_defaults.h.
It can be re-written independently for each Function from the local
management bus.
17-16R2R0hReserved
15RBERR/W1hEnables role-based error reporting.
It is hardwired to 1.It can be re-written
independently for each Function from the local management bus.
14-12R1R0hReserved
11-9AL1SLR/W0hSpecifies acceptable latency that the Endpoint can tolerate while transitioning from
L1 to L0.
It is set by default to the value define in reg_defaults.h.
It can be re-written
independently for each Function from the local management bus.
8-6AL0SLR/W4hSpecifies acceptable latency that the Endpoint can tolerate while transitioning from
L0S to L0.
It is set by default to the value define in reg_defaults.h.
It can be re-written
independently for each Function from the local management bus.
5ETFSR0hExtended Tag Field not Supported.
Hard coded to 0.
4-3PFSR0hThis field is used to extend the tag field by combining unused Function bits with the
tag bits.
This field is hardwired to 00 to disable this feature.
2-0MPSR/W1hSpecifies maximum payload size supported by the device.

3.5.1.34 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS Register (Offset = C8h + formula) [reset = 2810h]

PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS is shown in Figure 12-1300 and described in Table 12-2538.

Return to the Summary Table.

This register contains control and status bits associated with the device implementing
this Function. All the read-write bits in this register can also be written from the local
management bus. Likewise, bits designated as RW1C can also be cleared by writing a 1 from the
local management bus.

Offset = C8h + (n * 1000h); where n = 0h to 5h

Table 12-2537 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00C8h + formula
Figure 12-1300 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS Register
3130292827262524
R4
R-0h
2322212019181716
R4TPAPDURDFEDNFEDCED
R-0hR-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
FLRMRRSENSEAPEPHETFE
R/W-0hR/W-2hR/W-1hR-0hR-0hR-0h
76543210
MPSEROEURREFERENFERECER
R/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2538 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-22R4R0hReserved
21TPR0hIndicates if any of the Non-Posted requests issued by the Function are still
pending.
20APDR0hSet when auxiliary power is detected by the device.
This is an unused field.
19URDR/W1C0hSet to 1 by the Controller when it receives an unsupported request, regardless of whether
its reporting is enabled or not.
18FEDR/W1C0hSet to 1 by the Controller when it detects a fatal error, regardless of whether error
reporting is enabled or not, and regardless of whether the error is masked.
17NFEDR/W1C0hSet to 1 by the Controller when it detects a non-fatal error, regardless of whether error
reporting is enabled or not, and regardless of whether the error is masked.
16CEDR/W1C0hSet to 1 by the Controller when it detects a correctable error, regardless of whether error
reporting is enabled or not, and regardless of whether the error is masked.
15FLRR/W0hWriting a 1 into this bit position generates a Function-Level Reset for the selected
Function.
This bit reads as 0.
14-12MRRSR/W2hSpecifies the maximum size allowed in read requests generated by the device.
11ENSR/W1hWhen set to 1, the device is allowed to set the No Snoop bit in initiated transactions
in which cache coherency is not needed.
10EAPR0hUsed only when device used aux power.
This field is hardwired to 0.
9EPHR0hThis field is hardwired to 0 as the Controller does not support this feature.
8ETFER0hEnables the extension of the tag field from 5 to 8 bits.
7-5MPSR/W0hSpecifies the maximum TLP payload size configured.
The device must be able to receive
a TLP of this maximum size, and should not generate TLPs larger than this value.
The
configuration program sets this field based on the maximum payload size in the Device
Capabilities Register, and the capability of the other side.
4EROR/W1hWhen set, this bit indicates that the device is allowed to set the Relaxed Ordering
bit in the Attributes field of transactions initiated from it, when the transactions do not
require Strong Ordering.
3EURRR/W0hEnables the sending of error messages by the Controller on receiving unsupported requests.
2EFERR/W0hEnables the sending of ERR_FATAL messages by the Controller on the detection of fatal
errors.
1ENFERR/W0hEnables the sending of ERR_NONFATAL messages by the Controller on the detection of non-fatal
errors.
0ECERR/W0hEnables the sending of ERR_COR messages by the Controller on the detection of correctable
errors.

3.5.1.35 PCIE_CORE_PFn_I_LINK_CAP Register (Offset = CCh + formula) [reset = 0041AC24h]

PCIE_CORE_PFn_I_LINK_CAP is shown in Figure 12-1301 and described in Table 12-2540.

Return to the Summary Table.

This register advertises the link-specific capabilities of the device incorporating the
PCIe Controller.

Offset = CCh + (n * 1000h); where n = 0h to 5h

Table 12-2539 PCIE_CORE_PFn_I_LINK_CAP Instances
Figure 12-1301 PCIE_CORE_PFn_I_LINK_CAP Register
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2540 PCIE_CORE_PFn_I_LINK_CAP Register Field Descriptions

3.5.1.36 PCIE_CORE_PFn_I_LINK_CTRL_STATUS Register (Offset = D0h + formula) [reset = 00210000h]

PCIE_CORE_PFn_I_LINK_CTRL_STATUS is shown in Figure 12-1302 and described in Table 12-2542.

Return to the Summary Table.

This register contains control and status bits specific to the PCI Express link. All the
read-write bits in this register can also be written from the local management bus.

Offset = D0h + (n * 1000h); where n = 0h to 5h

Table 12-2541 PCIE_CORE_PFn_I_LINK_CTRL_STATUS Instances
Figure 12-1302 PCIE_CORE_PFn_I_LINK_CTRL_STATUS Register
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2542 PCIE_CORE_PFn_I_LINK_CTRL_STATUS Register Field Descriptions

3.5.1.37 PCIE_CORE_PFn_RSVD_035 Register (Offset = D4h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_035 is shown in Figure 12-1303 and described in Table 12-2544.

Return to the Summary Table.

Reserved

Offset = D4h + (n * 1000h); where n = 0h to 5h

Table 12-2543 PCIE_CORE_PFn_RSVD_035 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00D4h + formula
Figure 12-1303 PCIE_CORE_PFn_RSVD_035 Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2544 PCIE_CORE_PFn_RSVD_035 Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.38 PCIE_CORE_PFn_RSVD_036 Register (Offset = D8h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_036 is shown in Figure 12-1304 and described in Table 12-2546.

Return to the Summary Table.

Reserved

Offset = D8h + (n * 1000h); where n = 0h to 5h

Table 12-2545 PCIE_CORE_PFn_RSVD_036 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00D8h + formula
Figure 12-1304 PCIE_CORE_PFn_RSVD_036 Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2546 PCIE_CORE_PFn_RSVD_036 Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.39 PCIE_CORE_PFn_RSVD_037_038 Register (Offset = DCh + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_037_038 is shown in Figure 12-1305 and described in Table 12-2548.

Return to the Summary Table.

Reserved

Offset = DCh + (n * 1000h); where n = 0h to 5h

Table 12-2547 PCIE_CORE_PFn_RSVD_037_038 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00DCh + formula
Figure 12-1305 PCIE_CORE_PFn_RSVD_037_038 Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2548 PCIE_CORE_PFn_RSVD_037_038 Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.40 PCIE_CORE_PFn_I_PCIE_DEV_CAP_2 Register (Offset = E4h + formula) [reset = X]

PCIE_CORE_PFn_I_PCIE_DEV_CAP_2 is shown in Figure 12-1306 and described in Table 12-2550.

Return to the Summary Table.

This register advertises the capabilities of the PCI Express device encompassing this
Function.

Offset = E4h + (n * 1000h); where n = 0h to 5h

Table 12-2549 PCIE_CORE_PFn_I_PCIE_DEV_CAP_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00E4h + formula
Figure 12-1306 PCIE_CORE_PFn_I_PCIE_DEV_CAP_2 Register
3130292827262524
R14
R-0h
2322212019181716
MEEPEEPSEXFSOPFFST10RST10CS
R/W-1hR/W-1hR-1hR/W-1hR-0hR/W-1h
15141312111098
R13RESERVEDTCSLMSR12BAOCS128BAOCS64
R-0hR/W-XR-0hR/W-1hR-0hR-0hR-0h
76543210
BAOCS32OPRSAFSCTDSCTR
R-0hR-0hR-0hR/W-1hR/W-2h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2550 PCIE_CORE_PFn_I_PCIE_DEV_CAP_2 Register Field Descriptions
BitFieldTypeResetDescription
31-24R14R0hReserved
23-22MEEPR/W1hIndicates the maximum number of End-End TLP Prefixes supported by the Function.
The supported
values are: 01b 1 End-End TLP Prefix 10b 2 End-End TLP Prefixes
21EEPSR/W1hIndicates whether the Function supports End-End TLP Prefixes.
A 1 in this field indicates that
the Function supports receiving TLPs containing End-End TLP Prefixes.
20EXFSR1hIndicates that the Function supports the
3-bit definition of the Fmt field in the TLP header.
This bit is hardwired to 1 for all Functions.
19-18OPFFSR/W1hA 1 in this bit position indicates that the Function supports the Optimized Buffer
Flush/Fill [OBFF] capability using message signaling.
17T10RSR0hIf set function supports
1-bit requester capability
otherwise, the function does not.
This bit can be disabled using local management register.
16T10CSR/W1hIf set function supports
1-bit completer capability
otherwise, the function does not.
This field can be modified using local management interface.
15-14R13R0hReserved
13RESERVEDR/WX
12TCSR0hHardwired to 0.
11LMSR/W1hA 1 in this bit position indicates that the Function supports the Latency Tolerance
Reporting [LTR] Capability.
This bit is set to 1 by default, but can be turned off for all
Physical Functions by writing into PF 0.
10R12R0hReserved
9BAOCS128R0hHardwired to 0.
8BAOCS64R0hHardwired to 0.
7BAOCS32R0hHardwired to 0.
6OPRSR0hAtomic OP routing supported.
5AFSR0hARI forwarding supported.
4CTDSR/W1hA 1 in this field indicates that the associated Function supports the capability to
turn off its Completion timeout.
This bit is set to 1 by default, but can be re-written
independently for each Function from the local management bus.
3-0CTRR/W2hSpecifies the Completion Timeout values supported by the device.
This field is set by
default to 0010 [10 ms - 250 ms].
The actual timeout values are in two programmable local management
registers, which allow the timeout settings of the two sub-ranges within Range B to be
programmed independently.

3.5.1.41 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS_2 Register (Offset = E8h + formula) [reset = 0h]

PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS_2 is shown in Figure 12-1307 and described in Table 12-2552.

Return to the Summary Table.

This register contains control and status bits associated with the device implementing
this Function.

Offset = E8h + (n * 1000h); where n = 0h to 5h

Table 12-2551 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00E8h + formula
Figure 12-1307 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS_2 Register
3130292827262524
R18
R-0h
2322212019181716
R18
R-0h
15141312111098
R18OBFFET10RER17LTRMEIDOCEIDORE
R-0hR/W-0hR-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
R16AOREAFECTDCTV
R-0hR-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2552 PCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
31-15R18R0hReserved
14-13OBFFER/W0hEnables the Optimized Buffer Flush/Fill [OBFF] capability in the device.
This field is
implemented only in PF 0.
Valid settings are 00 [disabled], 01 [Variation A] and 10 [Variation
B].
This field can also be written from the local management bus.
RW if OBFF capability is
supported, RO otherwise.
12T10RER0h10bit TAGs generation are not supported in this configuration.
11R17R0hReserved
10LTRMER/W0hThis must be set to 1 to enable the Latency Tolerance Reporting Mechanism.
This bit is
implemented only in PF 0.
Its default value is 1, but can be modified from the local
management bus.
This bit is read-only in PF 1.
9IDOCER/W0hWhen this bit is 1, the Function is allowed to set the ID-based Ordering [IDO]
Attribute bit in the Completions it generates.
8IDORER/W0hWhen this bit is 1, the Function is allowed to set the ID-based Ordering [IDO]
Attribute bit in the requests it generates.
7R16R0hReserved
6AORER0hThis bit must be set to enable the generation of Atomic Op Requests from the Function.
If the client logic attempts to send an Atomic Op for a Function for which this bit is not set,
logic in the Controller will nullify the TLP on its way to the link.

5AFER0hARI forwarding enable
4CTDR/W0hSetting this bit disables Completion Timeout in the device.
This bit can also be
written from the local management bus.
3-0CTVR/W0hSpecifies the Completion Timeout value for the device.
Allowable values are 0101
[sub-range 1] and 0110 [sub-range 2].
The corresponding timeout values are stored in the local
management registers Completion Timeout Interval Registers 0 and 1, respectively.
Value of 0
selects completion timeout from Completion-Timeout-Interval-Registers-0 in local management
register.

3.5.1.42 PCIE_CORE_PFn_I_LINK_CAP_2_REG Register (Offset = ECh + formula) [reset = X]

PCIE_CORE_PFn_I_LINK_CAP_2_REG is shown in Figure 12-1308 and described in Table 12-2554.

Return to the Summary Table.

This register advertises the supported link speeds of the Controller.

Offset = ECh + (n * 1000h); where n = 0h to 5h

Table 12-2553 PCIE_CORE_PFn_I_LINK_CAP_2_REG Instances
Figure 12-1308 PCIE_CORE_PFn_I_LINK_CAP_2_REG Register
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2554 PCIE_CORE_PFn_I_LINK_CAP_2_REG Register Field Descriptions

3.5.1.43 PCIE_CORE_PFn_I_LINK_CTRL_STATUS_2 Register (Offset = F0h + formula) [reset = 00010004h]

PCIE_CORE_PFn_I_LINK_CTRL_STATUS_2 is shown in Figure 12-1309 and described in Table 12-2556.

Return to the Summary Table.

This register contains control and status bits specific to the PCI Express link. All the
fields marked RW or RW(STICKY) can also be written from the local management bus.

Offset = F0h + (n * 1000h); where n = 0h to 5h

Table 12-2555 PCIE_CORE_PFn_I_LINK_CTRL_STATUS_2 Instances
Figure 12-1309 PCIE_CORE_PFn_I_LINK_CTRL_STATUS_2 Register
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2556 PCIE_CORE_PFn_I_LINK_CTRL_STATUS_2 Register Field Descriptions

3.5.1.44 PCIE_CORE_PFn_RSVD_03D_03F Register (Offset = F4h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_03D_03F is shown in Figure 12-1310 and described in Table 12-2558.

Return to the Summary Table.

Reserved

Offset = F4h + (n * 1000h); where n = 0h to 5h

Table 12-2557 PCIE_CORE_PFn_RSVD_03D_03F Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 00F4h + formula
Figure 12-1310 PCIE_CORE_PFn_RSVD_03D_03F Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2558 PCIE_CORE_PFn_RSVD_03D_03F Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.45 PCIE_CORE_PFn_I_AER_ENHANCED_CAP_HDR Register (Offset = 100h + formula) [reset = 14020001h]

PCIE_CORE_PFn_I_AER_ENHANCED_CAP_HDR is shown in Figure 12-1311 and described in Table 12-2560.

Return to the Summary Table.

This is the first register in the PCI Express Advanced Error Reporting Capability
Structure. This register contains the PCI Express Extended Capability ID, the capability
version, and the pointer to the next capability structure.

Offset = 100h + (n * 1000h); where n = 0h to 5h

Table 12-2559 PCIE_CORE_PFn_I_AER_ENHANCED_CAP_HDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0100h + formula
Figure 12-1311 PCIE_CORE_PFn_I_AER_ENHANCED_CAP_HDR Register
313029282726252423222120191817161514131211109876543210
NCOCVPEECI
R/W-140hR/W-2hR-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2560 PCIE_CORE_PFn_I_AER_ENHANCED_CAP_HDR Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W140hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W2hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 4'h2, but can be modified from the local management bus.
15-0PEECIR1hThis field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express
AER Extended Capability Structure [0001 hex].

3.5.1.46 PCIE_CORE_PFn_I_UNCORR_ERR_STATUS Register (Offset = 104h + formula) [reset = 0h]

PCIE_CORE_PFn_I_UNCORR_ERR_STATUS is shown in Figure 12-1312 and described in Table 12-2562.

Return to the Summary Table.

This register provides the status of the various uncorrectable errors detected by the
PCI Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit
position. The states of the bits in the Uncorrectable Error Mask Register have no effect on the
status bits of this register. The setting of an uncorrectable error status bit causes the Controller
to generate an ERR_FATAL message if the corresponding severity bit of the Uncorrectable Error
Severity Register is 1. If the severity bit is 0, however, there are two separate ways the error
could be processed: (i) In certain cases, the uncorrectable error is treated as an Advisory
Non-Fatal Error. These cases are treated as similar to correctable errors, causing the Controller to
generate an ERR_COR message instead of an ERR_NONFATAL message. For details on these special
cases, refer to Section 6.2.3.2.4 of the PCI Express Base Specifications, Version 1.1. (ii) In
all other cases, the Controller sends an ERR_NONFATAL message when the error is detected. In all
cases, the sending of the error message can be suppressed by setting the bit corresponding to
the error type in the Uncorrectable Error Mask Register. For errors that are not
Function-specific, the error status bus is set in the registers belonging to all the Functions
associated with the link, but only a single message is generated for the entire link. In the
case of certain errors detected by the Transaction Layer, the associated TLP header is logged in
the Header Log Registers. All the RW1C bits can also be cleared from the local management bus by
writing a 1 into the bit position.

Offset = 104h + (n * 1000h); where n = 0h to 5h

Table 12-2561 PCIE_CORE_PFn_I_UNCORR_ERR_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0104h + formula
Figure 12-1312 PCIE_CORE_PFn_I_UNCORR_ERR_STATUS Register
3130292827262524
R3
R-0h
2322212019181716
R3UIER2URESEESMTSROSUCS
R-0hR/W1C-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
CASCTSFCPESPTSR1
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR-0h
76543210
R1SDESDLPESR0LTE
R-0hR/W1C-0hR/W1C-0hR-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2562 PCIE_CORE_PFn_I_UNCORR_ERR_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-23R3R0hN/A
22UIER/W1C0hThis bit is set when the Controller has detected an internal uncorrectable error [HAL parity
error or an uncorrectable ECC error while reading from any of the RAMs].
This bit is also set
in response to the client signaling an internal error through the input
UNCORRECTABLE_ERROR_IN.
This error is not Function-specific.
This error is considered fatal by
default, and is reported by sending an ERR_FATAL message.
STICKY.
21R2R0hReserved
20URESR/W1C0hThis bit is set when the Controller has received a request from the link that it does not
support.
This error is not Function-specific.
This error is considered non-fatal by default.
In the special case described in Sections 6.2.3.2.4.1 of the PCI Express Specifications, the
error is reported by sending an ERR_COR message.
In all other cases, the error is reported by
sending an ERR_NONFATAL message.
The header of the received request that caused the error is
logged in the Header Log Registers.
STICKY.
19EESR/W1C0hThis bit is set when the Controller has detected an ECRC error in a received TLP.
This error
is not Function-specific.
The header of the received TLP with error is logged in the Header Log
Registers.
STICKY.
18MTSR/W1C0hThis bit is set when the Controller receives a malformed TLP from the link.
This error is
not Function-specific.
This error is considered fatal by default, and is reported by sending
an ERR_FATAL message.
The header of the received TLP with error is logged in the Header Log
Registers.
STICKY.
17ROSR/W1C0hThis bit is set when the Controller receives a TLP in violation of the receive credit
currently available.
This error is not Function-specific.
STICKY.
16UCSR/W1C0hThis bit is set when the Controller has received an unexpected Completion packet from the
link.
This error is not Function-specific.
STICKY.
15CASR/W1C0hThis bit is set when the Controller has returned the Completer Abort [CA] status to a
request received from the link.
This error is Function-specific.
The header of the received
request that caused the error is logged in the Header Log Registers.
STICKY.
14CTSR/W1C0hThis bit is set when the completion timer associated with an outstanding request times
out.
This error is Function-specific.
This error is considered non-fatal by default.
STICKY.
13FCPESR/W1C0hThis bit is set when certain violations of the flow control protocol are detected by the Controller.
Controller reports FCPE upon the following conditions:
[i] InitFC/UpdateFC DLLP received which issues more than 2047 cumulative outstanding unused credits to the Transmitter for data payload or 127 for header.
[ii] InitFC_P is received with Payload Credits less than 128B, Or
[iii]InitFC_CPL is received with Payload Credits less than 128B.
This error is not Function-specific STICKY.
12PTSR/W1C0hThis bit is set when the Controller receives a poisoned TLP from the link.
This error is
Function-specific.
This error is considered non-fatal by default.
The error is reported by
sending an ERR_NONFATAL message.
The header of the received TLP with error is logged in the
Header Log Registers.
STICKY.
11-6R1R0hReserved
5SDESR/W1C0hThis error status indicates Link up to Link down event.
So Status bit is set upon LINK_DOWN_RESET_OUT event.
This field is applicable to RC only and not for EP as per PCIE spec.
4DLPESR/W1C0hThis bit is set when the Controller receives an Ack or Nak DLLP whose sequence number does
not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP [for
details, refer to PCI Express Base Specification 1.1, Section 3.5.2].
This error is not
Function-specific, and is reported by Function 0.
STICKY.
3-1R0R0hReserved
0LTER/W1C0hThis error indicates that link training is not successful and transition back to detect state.
This Status bit is set on any LTSSM transition from Configuration to Detect or Recovery to Detect.
This field is applicable to RC only and not for EP as per PCIE spec.

3.5.1.47 PCIE_CORE_PFn_I_UNCORR_ERR_MASK Register (Offset = 108h + formula) [reset = 00400000h]

PCIE_CORE_PFn_I_UNCORR_ERR_MASK is shown in Figure 12-1313 and described in Table 12-2564.

Return to the Summary Table.

The mask bits in this register control the reporting of uncorrectable errors. For each
error type in the Uncorrectable Error Status Register, there is a corresponding bit in this
register to mask its reporting. Setting the mask bit has the following effects: (i) The
occurrence of the error is not reported to the Root Complex (by a PCI Express error message).
(ii) The header of the TLP in which the error was detected is not logged in the Header Log
Registers. (iii) The First Error Pointer in the Advanced Error Capabilities and Control Register
is not updated on detection of the error. The individual bits of the mask register are described
below. The bits marked RW can also be written from the local management bus.

Offset = 108h + (n * 1000h); where n = 0h to 5h

Table 12-2563 PCIE_CORE_PFn_I_UNCORR_ERR_MASK Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0108h + formula
Figure 12-1313 PCIE_CORE_PFn_I_UNCORR_ERR_MASK Register
3130292827262524
R7
R-0h
2322212019181716
R7UIEMR6UREMEEMMTMROMUCM
R-0hR/W-1hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CAMCTMFCPEMPTMR5
R/W-0hR/W-0hR/W-0hR/W-0hR-0h
76543210
R5SDESMDLPEMR4LTEM
R-0hR/W-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2564 PCIE_CORE_PFn_I_UNCORR_ERR_MASK Register Field Descriptions
BitFieldTypeResetDescription
31-23R7R0hReserved
22UIEMR/W1hThis bit is set to mask the reporting of internal errors.
STICKY.
21R6R0hReserved
20UREMR/W0hThis bit is set to mask the reporting of unexpected requests received from the link.
STICKY.
19EEMR/W0hThis bit is set to mask the reporting of ECRC errors.
STICKY.
18MTMR/W0hThis bit is set to mask the reporting of malformed TLPs received from the link.
STICKY.
17ROMR/W0hThis bit is set to mask the reporting of violations of receive credit.
STICKY.
16UCMR/W0hThis bit is set to mask the reporting of unexpected Completions received by the
Controller.
STICKY.
15CAMR/W0hThis bit is set to mask the reporting of the Controller sending a Completer Abort.
STICKY.
14CTMR/W0hThis bit is set to mask the reporting of Completion Timeouts.
STICKY.
13FCPEMR/W0hThis bit is set to mask the reporting of Flow Control Protocol Errors.
STICKY.
12PTMR/W0hThis bit is set to mask the reporting of a Poisoned TLP.
STICKY.
11-6R5R0hReserved
5SDESMR/W0hThis bit is set to mask the reporting of Surprise Down Error Status Mask.
STICKY.
This field is applicable to RC only and not for EP as per PCIE spec.
4DLPEMR/W0hThis bit is set to mask the reporting of Data Link Protocol Errors.
STICKY.
3-1R4R0hReserved
0LTEMR/W0hThis bit is set to mask the reporting of Link Training Error Mask.
STICKY.
This field is applicable to RC only and not for EP as per PCIE-spec.

3.5.1.48 PCIE_CORE_PFn_I_UNCORR_ERR_SEVERITY Register (Offset = 10Ch + formula) [reset = 00462030h]

PCIE_CORE_PFn_I_UNCORR_ERR_SEVERITY is shown in Figure 12-1314 and described in Table 12-2566.

Return to the Summary Table.

The setting of this register determines whether an uncorrectable error is reported as a
fatal error on non-fatal error to the Root Complex. If a severity bit of this register is 0, the
corresponding error is reported by the Controller using an ERR_NONFATAL message. Otherwise, it is
reported using an ERR_FATAL message. The bits marked RW can also be written from the local
management bus.

Offset = 10Ch + (n * 1000h); where n = 0h to 5h

Table 12-2565 PCIE_CORE_PFn_I_UNCORR_ERR_SEVERITY Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 010Ch + formula
Figure 12-1314 PCIE_CORE_PFn_I_UNCORR_ERR_SEVERITY Register
3130292827262524
R12
R-0h
2322212019181716
R12UIESR11URESEESMTSROSUCS
R-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
CASCTSFCPESPTSR10
R/W-0hR/W-0hR/W-1hR/W-0hR-0h
76543210
R10SDESDLPERR8LTES
R-0hR/W-1hR/W-1hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2566 PCIE_CORE_PFn_I_UNCORR_ERR_SEVERITY Register Field Descriptions
BitFieldTypeResetDescription
31-23R12R0hReserved
22UIESR/W1hSeverity of internal errors
[0 = Non-Fatal,
1 = Fatal].
STICKY.
21R11R0hReserved
20URESR/W0hSeverity of unexpected requests received from the link
[0 = Non-Fatal,
1 = Fatal].
STICKY.
19EESR/W0hSeverity of ECRC errors
[0 = Non-Fatal,
1 = Fatal].
STICKY.
18MTSR/W1hSeverity of malformed TLPs received from the link
[0 = Non- Fatal,
1 = Fatal].
STICKY.
17ROSR/W1hSeverity of receive credit violations
[0 = Non-Fatal,
1 = Fatal].
STICKY.
16UCSR/W0hSeverity of unexpected Completions received by the Controller
[0 = Non-Fatal,
1 = Fatal].
STICKY.
15CASR/W0hSeverity of sending a Completer Abort
[0 = Non-Fatal,
1 = Fatal].
STICKY.
14CTSR/W0hSeverity of Completion Timeouts
[0 = Non-Fatal,
1 = Fatal].
STICKY.
13FCPESR/W1hSeverity of Flow Control Protocol Errors
[0 = Non-Fatal,
1 = Fatal].
STICKY.
12PTSR/W0hSeverity of a Poisoned TLP error
[0 = Non-Fatal,
1 = Fatal].
STICKY.
11-6R10R0hReserved
5SDESR/W1hSeverity of Surprise Down Error Severity [0 = Non-Fatal, 1 = Fatal].
STICKY.
This field is applicable to RC only and not for EP as per PCIE spec.
4DLPERR/W1hSeverity of Data Link Protocol Errors
[0 = Non-Fatal,
1 = Fatal].
STICKY.
3-1R8R0hReserved
0LTESR/W0hSeverity of Link Training Error [0 = Non-Fatal, 1 = Fatal].
STICKY.
This field is applicable to RC only and not for EP as per PCIE spec.

3.5.1.49 PCIE_CORE_PFn_I_CORR_ERR_STATUS Register (Offset = 110h + formula) [reset = 0h]

PCIE_CORE_PFn_I_CORR_ERR_STATUS is shown in Figure 12-1315 and described in Table 12-2568.

Return to the Summary Table.

This register provides the status of the various correctable errors detected by the PCI
Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit
position. The states of the bits in the Correctable Error Mask Register have no effect on the
status bits of this register. The setting of a correctable error status bit causes the Controller to
generate an ERR_COR error message to the Root Complex if the error is not masked in the
Correctable Error Mask Register. For errors that are not Function-specific, the error status bus
is set in the registers belonging to all the Functions associated with the link, but only a
single message is generated for the entire link. Header logging of received TLPs does not apply
to correctable errors. All the RW1C bits can also be cleared from the local management bus by
writing a 1 into the bit position.

Offset = 110h + (n * 1000h); where n = 0h to 5h

Table 12-2567 PCIE_CORE_PFn_I_CORR_ERR_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0110h + formula
Figure 12-1315 PCIE_CORE_PFn_I_CORR_ERR_STATUS Register
3130292827262524
R14
R-0h
2322212019181716
R14
R-0h
15141312111098
HLOSCIESANFESRTTSR13RNRS
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR-0hR/W1C-0h
76543210
BDSBTSR12RES
R/W1C-0hR/W1C-0hR-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2568 PCIE_CORE_PFn_I_CORR_ERR_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-16R14R0hReserved
15HLOSR/W1C0hThis bit is set on a Header Log Register overflow, that is, when the header could not
be logged in the Header Log Register because it is occupied by a previous header.
STICKY.
14CIESR/W1C0hThis bit is set when the Controller has detected an internal correctable error condition [a
correctable ECC error while reading from any of the RAMs].
This bit is also set in response to
the client signaling an internal error through the input CORRECTABLE_ERROR_IN.
This error is
not Function-specific.
STICKY.
13ANFESR/W1C0hThis bit is set when an uncorrectable error occurs, which is determined to belong to
one of the special cases described in Section 6.2.3.2.4 of the PCI Express 2.0 Specifications.
This causes the Controller to generate an ERR_COR message in place of an ERR_NONFATAL message.
STICKY.
12RTTSR/W1C0hThis bit is set when the replay timer in the Data Link Layer of the Controller times out,
causing the Controller to retransmit a TLP.
This error is not Function-specific.
STICKY.
11-9R13R0hReserved
8RNRSR/W1C0hThis bit is set when the replay count rolls over after three re-transmissions of a TLP
at the Data Link Layer of the Controller.
This error is not Function-specific STICKY.
7BDSR/W1C0hThis bit is set when an LCRC error is detected in a received DLLP, and no errors were
detected by the Physical Layer.
This error is not Function-specific.
STICKY.
6BTSR/W1C0hThis bit is set when an error is detected in a received TLP by the Data Link Layer of
the Controller.
The conditions causing this error are: [i] An LCRC error [ii] The packet terminates
with EDB symbol, but its LCRC field does not equal the inverted value of the calculated CRC.
This error is not Function-specific.
STICKY.
5-1R12R0hReserved
0RESR/W1C0hThis bit is set when an error is detected in the receive side of the Physical Layer of
the Controller [e.g.
a bit error or coding violation].

This bit is set upon any of the following errors:
[1] PHY reported 8B10B error, Disparity Error, Elastic Buffer Overflow Error, Underflow Error
[2] GEN3 TLP, DLLP Framing Errors
[3] OS Block Received Without EDS
[4] Data Block Received After EDS
[5] Illegal OS Block After EDS
[6] OS Block Received After SKIP OS
[7] OS Block Received After SDS
[8] Sync Header Error
[9] Loss of Gen3 Block Alignment
This error is not Function-specific.
STICKY.

3.5.1.50 PCIE_CORE_PFn_I_CORR_ERR_MASK Register (Offset = 114h + formula) [reset = E000h]

PCIE_CORE_PFn_I_CORR_ERR_MASK is shown in Figure 12-1316 and described in Table 12-2570.

Return to the Summary Table.

The mask bits in this register control the reporting of correctable errors. For each
error type in the Correctable Error Status Register, there is a corresponding bit in this
register to mask its reporting. When a mask bit is set, the occurrence of the error is not
reported to the Root Complex (by a PCI Express error message). The individual bits of the mask
register are described below. The bits marked RW can also be written from the local management
bus.

Offset = 114h + (n * 1000h); where n = 0h to 5h

Table 12-2569 PCIE_CORE_PFn_I_CORR_ERR_MASK Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0114h + formula
Figure 12-1316 PCIE_CORE_PFn_I_CORR_ERR_MASK Register
3130292827262524
R17
R-0h
2322212019181716
R17
R-0h
15141312111098
HLOMCIEMANFEMRTTMR16RNRM
R/W-1hR/W-1hR/W-1hR/W-0hR-0hR/W-0h
76543210
BDMBTMR15REM
R/W-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2570 PCIE_CORE_PFn_I_CORR_ERR_MASK Register Field Descriptions
BitFieldTypeResetDescription
31-16R17R0hReserved
15HLOMR/W1hThis bit, when set, masks the generation of error messages in response to a Header Log
register overflow.
STICKY.
14CIEMR/W1hThis bit, when set, masks the generation of error messages in response to a corrected
internal error condition.
STICKY.
13ANFEMR/W1hThis bit, when set, masks the generation of error messages in response to an
uncorrectable error occur, which is determined to belong to one of the special cases [as
described in Section 6.2.3.2.4 of the PCI Express 2.0 Specifications].
STICKY.
12RTTMR/W0hThis bit, when set, masks the generation of error messages in response to a Replay
Timer timeout event.
STICKY.
11-9R16R0hReserved
8RNRMR/W0hThis bit, when set, masks the generation of error messages in response to a Replay
Number Rollover event.
STICKY.
7BDMR/W0hThis bit, when set, masks the generation of error messages in response to a 'Bad DLLP'
received.
STICKY.
6BTMR/W0hThis bit, when set, masks the generation of error messages in response to a 'Bad TLP'
received.
STICKY.
5-1R15R0hReserved
0REMR/W0hThis bit, when set, masks the generation of error messages in response to the Physical
Layer errors STICKY.

3.5.1.51 PCIE_CORE_PFn_I_ADVCD_ERR_CAP_CTRL Register (Offset = 118h + formula) [reset = A0h]

PCIE_CORE_PFn_I_ADVCD_ERR_CAP_CTRL is shown in Figure 12-1317 and described in Table 12-2572.

Return to the Summary Table.

This register contains a pointer to the first error that is reported in the
Uncorrectable Error Status Register, and bits to enable ECRC generation and checking.

Offset = 118h + (n * 1000h); where n = 0h to 5h

Table 12-2571 PCIE_CORE_PFn_I_ADVCD_ERR_CAP_CTRL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0118h + formula
Figure 12-1317 PCIE_CORE_PFn_I_ADVCD_ERR_CAP_CTRL Register
3130292827262524
R18
R-0h
2322212019181716
R18
R-0h
15141312111098
R18TPLPMHREMHRCEEC
R-0hR-0hR-0hR-0hR/W-0h
76543210
ECCEEGEGCFER
R/W-1hR/W-0hR/W-1hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2572 PCIE_CORE_PFn_I_ADVCD_ERR_CAP_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-12R18R0hReserved
11TPLPR0hIf Set and the First Error
Pointer is valid, indicates that the TLP Prefix Log
register contains valid information.
If Clear or if First
Error Pointer is invalid, the TLP Prefix Log register
is undefined.
Default value of this bit is 0.
This bit is RsvdP if the
End-End TLP Prefix Supported bit is CIf Set and the First Error
Pointer is valid, indicates that the TLP Prefix Log
register contains valid information.
If Clear or if First
Error Pointer is invalid, the TLP Prefix Log register
is undefined.
10MHRER0hSetting this bit enables the Function to log multiple error headers in its Header
Log Registers.
It is hardwired to 0
9MHRCR0hThis bit is set when the Function has the capability to log more than one error
header in its Header Log Registers.
It is hardwired to 0.
8EECR/W0hSetting this bit enables ECRC checking on the receive side of the Controller.
This bit is
writable from the local management bus.
STICKY.
7ECCR/W1hThis read-only bit indicates to the software that the device is capable of checking
ECRC in packets received from the link.
This bit is writable from the local management bus.
6EEGR/W0hSetting this bit enables the ECRC generation on the transmit side of the Controller.
This
bit is writable from the local management bus.
STICKY.
5EGCR/W1hThis read-only bit indicates to the software that the device is capable of generating
ECRC in packets transmitted on the link.
This bit is writable from the local management
bus.
4-0FERR0hThis is a
5-bit pointer to the bit position in the Uncorrectable Error Status Register
corresponding to the error that was detected first.
When there are multiple bits set in the
Uncorrectable Error Status Register, this field informs the software which error was observed
first.
To prevent the field from being overwritten before software was able to read it, this
field is not updated while the status bit pointed by it in the Uncorrectable Error Status
Register remains set.
After the software clears this status bit, a subsequent error condition
that sets any bit in the Uncorrectable Error Status Register will update the First Error
Pointer.
Any uncorrectable error type, including the special cases where the error is reported
using an ERR_COR message, will set the First Error Pointer [assuming the software has reset
the error pointed by it in the Uncorrectable Error Status Register].
STICKY.

3.5.1.52 PCIE_CORE_PFn_I_HDR_LOG_0 Register (Offset = 11Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_HDR_LOG_0 is shown in Figure 12-1318 and described in Table 12-2574.

Return to the Summary Table.

This is the first of a set of four registers used to capture the header of a TLP
received by the Controller from the link upon detection of an uncorrectable error. When multiple
bits are set in the Uncorrectable Error Status Register, the captured header corresponds to
the error that was detected first, that is, the error pointed by the First Error Pointer. To
prevent the captured header from being over-written before software was able to read it, this
register is not updated while the status bit pointed by the First Error Pointer in the
Uncorrectable Error Status Register remains set. After the software clears this status bit, a
subsequent error condition that sets any bit in the Uncorrectable Error Status Register will
also cause the Header Log Registers to be updated. The doublewords of the TLP header are
stored in the Header Log Registers with their bytes transposed. That is, the byte containing
the Type/Format fields of the header is stored at bit positions 31:24 of the Header Log
Register 0.

Offset = 11Ch + (n * 1000h); where n = 0h to 5h

Table 12-2573 PCIE_CORE_PFn_I_HDR_LOG_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 011Ch + formula
Figure 12-1318 PCIE_CORE_PFn_I_HDR_LOG_0 Register
313029282726252423222120191817161514131211109876543210
HD0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2574 PCIE_CORE_PFn_I_HDR_LOG_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0HD0R0hFirst DWORD of captured TLP header STICKY.

3.5.1.53 PCIE_CORE_PFn_I_HDR_LOG_1 Register (Offset = 120h + formula) [reset = 0h]

PCIE_CORE_PFn_I_HDR_LOG_1 is shown in Figure 12-1319 and described in Table 12-2576.

Return to the Summary Table.

This register contains the second DWORD of the captured TLP header. The bytes are
stored in transposed order.

Offset = 120h + (n * 1000h); where n = 0h to 5h

Table 12-2575 PCIE_CORE_PFn_I_HDR_LOG_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0120h + formula
Figure 12-1319 PCIE_CORE_PFn_I_HDR_LOG_1 Register
313029282726252423222120191817161514131211109876543210
HD1
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2576 PCIE_CORE_PFn_I_HDR_LOG_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0HD1R0hSecond DWORD of captured TLP header STICKY.

3.5.1.54 PCIE_CORE_PFn_I_HDR_LOG_2 Register (Offset = 124h + formula) [reset = 0h]

PCIE_CORE_PFn_I_HDR_LOG_2 is shown in Figure 12-1320 and described in Table 12-2578.

Return to the Summary Table.

This register contains the third DWORD of the captured TLP header. The bytes are
stored in transposed order.

Offset = 124h + (n * 1000h); where n = 0h to 5h

Table 12-2577 PCIE_CORE_PFn_I_HDR_LOG_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0124h + formula
Figure 12-1320 PCIE_CORE_PFn_I_HDR_LOG_2 Register
313029282726252423222120191817161514131211109876543210
HD2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2578 PCIE_CORE_PFn_I_HDR_LOG_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0HD2R0hThird DWORD of captured TLP header STICKY.

3.5.1.55 PCIE_CORE_PFn_I_HDR_LOG_3 Register (Offset = 128h + formula) [reset = 0h]

PCIE_CORE_PFn_I_HDR_LOG_3 is shown in Figure 12-1321 and described in Table 12-2580.

Return to the Summary Table.

If the captured TLP header is 4 DWORDs long, this register contains its fourth DWORD. If
the captured header is a 3-DWORD header, this register is unused. The bytes of the DWORD are
stored in this register in transposed order.

Offset = 128h + (n * 1000h); where n = 0h to 5h

Table 12-2579 PCIE_CORE_PFn_I_HDR_LOG_3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0128h + formula
Figure 12-1321 PCIE_CORE_PFn_I_HDR_LOG_3 Register
313029282726252423222120191817161514131211109876543210
HD3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2580 PCIE_CORE_PFn_I_HDR_LOG_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0HD3R0hFourth DWORD of captured TLP header STICKY.

3.5.1.56 PCIE_CORE_PFn_RSVD_04B_04D Register (Offset = 12Ch + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_04B_04D is shown in Figure 12-1322 and described in Table 12-2582.

Return to the Summary Table.

Reserved

Offset = 12Ch + (n * 1000h); where n = 0h to 5h

Table 12-2581 PCIE_CORE_PFn_RSVD_04B_04D Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 012Ch + formula
Figure 12-1322 PCIE_CORE_PFn_RSVD_04B_04D Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2582 PCIE_CORE_PFn_RSVD_04B_04D Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.57 PCIE_CORE_PFn_I_TLP_PRE_LOG_0 Register (Offset = 138h + formula) [reset = 0h]

PCIE_CORE_PFn_I_TLP_PRE_LOG_0 is shown in Figure 12-1323 and described in Table 12-2584.

Return to the Summary Table.

First TLP Prefix (if present) associated with the TLP whose header is in the Header Log Register.
The bytes are in transposed order.

Offset = 138h + (n * 1000h); where n = 0h to 5h

Table 12-2583 PCIE_CORE_PFn_I_TLP_PRE_LOG_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0138h + formula
Figure 12-1323 PCIE_CORE_PFn_I_TLP_PRE_LOG_0 Register
313029282726252423222120191817161514131211109876543210
HD1
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2584 PCIE_CORE_PFn_I_TLP_PRE_LOG_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0HD1R0hFirst TLP Prefix of captured TLP STICKY.

3.5.1.58 PCIE_CORE_PFn_I_ARI_EXT_CAP_HDR Register (Offset = 140h + formula) [reset = 1501000Eh]

PCIE_CORE_PFn_I_ARI_EXT_CAP_HDR is shown in Figure 12-1324 and described in Table 12-2586.

Return to the Summary Table.

This register is used to enable
the Alternate Routing ID interpretation. This register contains the PCI Express Extended
Capability ID, the capability version, and the pointer to the next capability structure.

Offset = 140h + (n * 1000h); where n = 0h to 5h

Table 12-2585 PCIE_CORE_PFn_I_ARI_EXT_CAP_HDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0140h + formula
Figure 12-1324 PCIE_CORE_PFn_I_ARI_EXT_CAP_HDR Register
31302928272625242322212019181716
ARINCOARICV
R/W-150hR/W-1h
1514131211109876543210
PECID
R-Eh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2586 PCIE_CORE_PFn_I_ARI_EXT_CAP_HDR Register Field Descriptions
BitFieldTypeResetDescription
31-20ARINCOR/W150hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16ARICVR/W1hSpecifies the SIG-assigned value for the version of the capability structure.
This
field is set to 1 by default, but can be modified independently for each Function from the
local management bus
15-0PECIDREhThis field is hardwired to the Capability ID assigned by PCI-SIG to the ARI Extended
Capability [000E hex].

3.5.1.59 PCIE_CORE_PFn_I_ARI_CAP_AND_CTRL Register (Offset = 144h + formula) [reset = X]

PCIE_CORE_PFn_I_ARI_CAP_AND_CTRL is shown in Figure 12-1325 and described in Table 12-2588.

Return to the Summary Table.

This location contains the ARI Capability Register and the ARI Control Register. The
individual fields are described below.

Offset = 144h + (n * 1000h); where n = 0h to 5h

Table 12-2587 PCIE_CORE_PFn_I_ARI_CAP_AND_CTRL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0144h + formula
Figure 12-1325 PCIE_CORE_PFn_I_ARI_CAP_AND_CTRL Register
3130292827262524
ACR
R-0h
2322212019181716
ACR
R-0h
15141312111098
NF
R/W-1h
76543210
RESERVEDAFGCMFGC
R/W-XR-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2588 PCIE_CORE_PFn_I_ARI_CAP_AND_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-16ACRR0hARI Control Register not implemented in this Controller.
This field is hardwired to 0.
15-8NFR/W1hPoints to the next Physical Function in the device.
This field is set by default to
point to the next Physical Function, 0 for last Function.
It can be rewritten from the local management bus.
7-2RESERVEDR/WX
1AFGCR0hRelevant only when ACS Capability is supported.
This field is hardwired to 0.
0MFGCR0hSet when device supports arbitration at the Function Group-level.
This field is
hardwired to 0.

3.5.1.60 PCIE_CORE_PFn_RSVD_052_053 Register (Offset = 148h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_052_053 is shown in Figure 12-1326 and described in Table 12-2590.

Return to the Summary Table.

Reserved

Offset = 148h + (n * 1000h); where n = 0h to 5h

Table 12-2589 PCIE_CORE_PFn_RSVD_052_053 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0148h + formula
Figure 12-1326 PCIE_CORE_PFn_RSVD_052_053 Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2590 PCIE_CORE_PFn_RSVD_052_053 Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.61 PCIE_CORE_PFn_I_DEV_SER_NUM_CAP_HDR Register (Offset = 150h + formula) [reset = 16010003h]

PCIE_CORE_PFn_I_DEV_SER_NUM_CAP_HDR is shown in Figure 12-1327 and described in Table 12-2592.

Return to the Summary Table.

This register contains the PCI Express Extended Capability ID for Device Serial Number
Capability, the capability version, and the pointer to the next capability structure.

Offset = 150h + (n * 1000h); where n = 0h to 5h

Table 12-2591 PCIE_CORE_PFn_I_DEV_SER_NUM_CAP_HDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0150h + formula
Figure 12-1327 PCIE_CORE_PFn_I_DEV_SER_NUM_CAP_HDR Register
31302928272625242322212019181716
SNNCODSNCV
R/W-160hR/W-1h
1514131211109876543210
PECID
R-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2592 PCIE_CORE_PFn_I_DEV_SER_NUM_CAP_HDR Register Field Descriptions
BitFieldTypeResetDescription
31-20SNNCOR/W160hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16DSNCVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified from the local management bus by writing
into Function 0 from the local management bus.
15-0PECIDR3hThis field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express
Device Serial Number Capability [0001 hex].

3.5.1.62 PCIE_CORE_PFn_I_DEV_SER_NUM_0 Register (Offset = 154h + formula) [reset = 0h]

PCIE_CORE_PFn_I_DEV_SER_NUM_0 is shown in Figure 12-1328 and described in Table 12-2594.

Return to the Summary Table.

This read-only register stored the first 32 bits of the device's serial number. Its
setting is common for all the Physical Functions, and can be modified by writing into this
register in Function 0 from the local management bus.

Offset = 154h + (n * 1000h); where n = 0h to 5h

Table 12-2593 PCIE_CORE_PFn_I_DEV_SER_NUM_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0154h + formula
Figure 12-1328 PCIE_CORE_PFn_I_DEV_SER_NUM_0 Register
313029282726252423222120191817161514131211109876543210
DSND0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2594 PCIE_CORE_PFn_I_DEV_SER_NUM_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DSND0R/W0hThis field contains the first 32 bits of the device's serial number.

3.5.1.63 PCIE_CORE_PFn_I_DEV_SER_NUM_1 Register (Offset = 158h + formula) [reset = 0h]

PCIE_CORE_PFn_I_DEV_SER_NUM_1 is shown in Figure 12-1329 and described in Table 12-2596.

Return to the Summary Table.

This read-only register stored the last 32 bits of the device's serial number. Its
setting is common for all the Physical Functions, and can be modified by writing into this
register in Function 0 from the local management bus.

Offset = 158h + (n * 1000h); where n = 0h to 5h

Table 12-2595 PCIE_CORE_PFn_I_DEV_SER_NUM_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0158h + formula
Figure 12-1329 PCIE_CORE_PFn_I_DEV_SER_NUM_1 Register
313029282726252423222120191817161514131211109876543210
DSND1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2596 PCIE_CORE_PFn_I_DEV_SER_NUM_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DSND1R/W0hThis field contains the last 32 bits of the device's serial number.

3.5.1.64 PCIE_CORE_PFn_RSVD_057 Register (Offset = 15Ch + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_057 is shown in Figure 12-1330 and described in Table 12-2598.

Return to the Summary Table.

Reserved

Offset = 15Ch + (n * 1000h); where n = 0h to 5h

Table 12-2597 PCIE_CORE_PFn_RSVD_057 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 015Ch + formula
Figure 12-1330 PCIE_CORE_PFn_RSVD_057 Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2598 PCIE_CORE_PFn_RSVD_057 Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.65 PCIE_CORE_PFn_I_PWR_BDGTG_ENHC_CAP_HDR Register (Offset = 160h + formula) [reset = 1B810004h]

PCIE_CORE_PFn_I_PWR_BDGTG_ENHC_CAP_HDR is shown in Figure 12-1331 and described in Table 12-2600.

Return to the Summary Table.

This register contains the PCI Express Extended Capability ID for Power Budgeting
Capability, its capability version, and the pointer to the next capability structure.

Offset = 160h + (n * 1000h); where n = 0h to 5h

Table 12-2599 PCIE_CORE_PFn_I_PWR_BDGTG_ENHC_CAP_HDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0160h + formula
Figure 12-1331 PCIE_CORE_PFn_I_PWR_BDGTG_ENHC_CAP_HDR Register
313029282726252423222120191817161514131211109876543210
PBNCOPCVPECID
R/W-1B8hR/W-1hR-4h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2600 PCIE_CORE_PFn_I_PWR_BDGTG_ENHC_CAP_HDR Register Field Descriptions
BitFieldTypeResetDescription
31-20PBNCOR/W1B8hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16PCVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified from the local management bus by writing
into Function 0 from the local management bus.
15-0PECIDR4hThis field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express
Power Budgeting Capability [0004 hex].

3.5.1.66 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_SEL Register (Offset = 164h + formula) [reset = 0h]

PCIE_CORE_PFn_I_PWR_BDGTG_DATA_SEL is shown in Figure 12-1332 and described in Table 12-2602.

Return to the Summary Table.

This register is used to select the specific word of specific power-budgeting data
returned on a read from the Power Budgeting Data Register. This version of the Controller stores power
budgeting data for three distinct power states (D0, D1 and D3hot ) for each Physical Function,
which can be read from the Power Budgeting Data Register by indexing through this register, as
described below.

Offset = 164h + (n * 1000h); where n = 0h to 5h

Table 12-2601 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_SEL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0164h + formula
Figure 12-1332 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_SEL Register
313029282726252423222120191817161514131211109876543210
R0PBDN
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2602 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-8R0R0hN/A
7-0PBDNR/W0hThis field selects the power budgeting data read from the Power Budgeting Data
Register.
Its settings are:

00: Selects power budgeting data for power state D0 MAX for the associated PF.


01: Selects power budgeting data for power state D0 SUSTAINED for the associated PF.

10: Selects power budgeting data for power state D3hot for the associated PF.


11: Selects power budgeting data for power state D1 for the associated PF.

Others: Not a valid setting.
A read from the Power Budgeting Data Register returns all zeroes.

3.5.1.67 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_REGISTER Register (Offset = 168h + formula) [reset = 000B80F0h]

PCIE_CORE_PFn_I_PWR_BDGTG_DATA_REGISTER is shown in Figure 12-1333 and described in Table 12-2604.

Return to the Summary Table.

This read-only register returns the DWORD of Power Budgeting Data selected by the Data Select
register. Each DWORD of the Power Budgeting Data describes the power usage of the device in a
particular operating condition. All the fields can be modified independently for each PF by writing from the
local management bus.

Offset = 168h + (n * 1000h); where n = 0h to 5h

Table 12-2603 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_REGISTER Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0168h + formula
Figure 12-1333 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_REGISTER Register
31302928272625242322212019181716
R1PRTYPE
R-0hR/W-2hR/W-7h
1514131211109876543210
TYPEPSPSSDSBP
R/W-7hR/W-0hR/W-0hR/W-0hR/W-F0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2604 PCIE_CORE_PFn_I_PWR_BDGTG_DATA_REGISTER Register Field Descriptions
BitFieldTypeResetDescription
31-21R1R0hReserved
20-18PRR/W2hSpecifies the power rail corresponding to the power management data in this
register.
17-15TYPER/W7hSpecifies the operation condition for which the data applies.
14-13PSR/W0hSpecifies the power management state of the Function, for which this power management
data applies.
12-10PSSR/W0hSpecifies the power management sub-state of the selected power state
9-8DSR/W0hScale factor applicable to the Base Power field.
7-0BPR/WF0hSpecifies base power[in watts] of the selected power state

3.5.1.68 PCIE_CORE_PFn_I_PWR_BDGT_CAP Register (Offset = 16Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_PWR_BDGT_CAP is shown in Figure 12-1334 and described in Table 12-2606.

Return to the Summary Table.

This register specifies whether the device power specified by this Capability Structure
is included in the system power budget.

Offset = 16Ch + (n * 1000h); where n = 0h to 5h

Table 12-2605 PCIE_CORE_PFn_I_PWR_BDGT_CAP Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 016Ch + formula
Figure 12-1334 PCIE_CORE_PFn_I_PWR_BDGT_CAP Register
31302928272625242322212019181716
R4
R-0h
1514131211109876543210
R4SA
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2606 PCIE_CORE_PFn_I_PWR_BDGT_CAP Register Field Descriptions
BitFieldTypeResetDescription
31-1R4R0hReserved
0SAR/W0hThis bit is set to indicate that the device power specified by this Power Management
Capability Structure is included in the system power budget.
When this bit set, the software
must exclude the device power reported by this Capability Structure from power calculations,
when making power budgeting decisions.
This bit is set to 0 by default, but its setting can be
modified individually for each PF from the local management bus.

3.5.1.69 PCIE_CORE_PFn_RSVD_05C_05F Register (Offset = 170h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_05C_05F is shown in Figure 12-1335 and described in Table 12-2608.

Return to the Summary Table.

Reserved

Offset = 170h + (n * 1000h); where n = 0h to 5h

Table 12-2607 PCIE_CORE_PFn_RSVD_05C_05F Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0170h + formula
Figure 12-1335 PCIE_CORE_PFn_RSVD_05C_05F Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2608 PCIE_CORE_PFn_RSVD_05C_05F Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.70 PCIE_CORE_PFn_I_RESIZE_BAR_EXT_CAP_HDR Register (Offset = 180h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_EXT_CAP_HDR is shown in Figure 12-1336 and described in Table 12-2610.

Return to the Summary Table.

This register contains the PCI Express Extended Capability ID for the Resizable BAR
Capability, its capability version, and the pointer to the next capability structure. This
register is enabled only when the Resizable BAR Capability is enabled for the Physical Function
by setting the Enable Resizable BAR Capability bit (bit 31) of the associated Physical Function
BAR Configuration Register (Section 8.4.2.24). When the Resizable BAR Capability is not enabled,
a read from this location returns all zeroes.

Offset = 180h + (n * 1000h); where n = 0h to 5h

Table 12-2609 PCIE_CORE_PFn_I_RESIZE_BAR_EXT_CAP_HDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0180h + formula
Figure 12-1336 PCIE_CORE_PFn_I_RESIZE_BAR_EXT_CAP_HDR Register
313029282726252423222120191817161514131211109876543210
NCOCVPECID
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2610 PCIE_CORE_PFn_I_RESIZE_BAR_EXT_CAP_HDR Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR0hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR0hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified from the local management bus.
15-0PECIDR0hThis field is hardwired to the Capability ID assigned by PCI SIG to the Resizable BAR
Capability [0015 hex].

3.5.1.71 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_0 Register (Offset = 184h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CAP_0 is shown in Figure 12-1337 and described in Table 12-2612.

Return to the Summary Table.

This register advertises the available aperture settings of the first memory BAR of the
associated Physical Function. This register is active only when the Resizable BAR Capability
is enabled for the Physical Function by setting the Enable Resizable BAR Capability (bit 31) of
the associated Physical Function BAR Configuration Register 1. When the Resizable BAR Capability
is not enabled, a read from this location returns all zeros. When the Resizable BAR Capability
is enabled, any of the bits 4-22 can be modified from the local management bus.

Offset = 184h + (n * 1000h); where n = 0h to 5h

Table 12-2611 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0184h + formula
Figure 12-1337 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_0 Register
3130292827262524
R1
R-0h
2322212019181716
A512GA256GA128GA64GA32GA16GA8GA4G
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
A2GA1GA512MA256MA128MA64MA32MA16M
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
A8MA4MA2MA1MR0
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2612 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_0 Register Field Descriptions
BitFieldTypeResetDescription
31-24R1R0hReserved
23A512GR0hIndicates that the BAR aperture can be set to 512G.
22A256GR0hIndicates that the BAR aperture can be set to 256G.
21A128GR0hIndicates that the BAR aperture can be set to 128G.
20A64GR0hIndicates that the BAR aperture can be set to 64G.
19A32GR0hIndicates that the BAR aperture can be set to 32G.
18A16GR0hIndicates that the BAR aperture can be set to 16G.
17A8GR0hIndicates that the BAR aperture can be set to 8G.
16A4GR0hIndicates that the BAR aperture can be set to 4G.
15A2GR0hIndicates that the BAR aperture can be set to 2G.
14A1GR0hIndicates that the BAR aperture can be set to 1G.
13A512MR0hIndicates that the BAR aperture can be set to 512M.
12A256MR0hIndicates that the BAR aperture can be set to 256M.
11A128MR0hIndicates that the BAR aperture can be set to 128M.
10A64MR0hIndicates that the BAR aperture can be set to 64M.
9A32MR0hIndicates that the BAR aperture can be set to 32M.
8A16MR0hIndicates that the BAR aperture can be set to 16M.
7A8MR0hIndicates that the BAR aperture can be set to 8M.
6A4MR0hIndicates that the BAR aperture can be set to 4M.
5A2MR0hIndicates that the BAR aperture can be set to 2M.
4A1MR0hIndicates that the BAR aperture can be set to 1M.
3-0R0R0hReserved

3.5.1.72 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_0 Register (Offset = 188h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_0 is shown in Figure 12-1338 and described in Table 12-2614.

Return to the Summary Table.

This register controls the aperture setting of the first memory BAR of the associated
Physical Function, and also has a field that specifies the number of resizable BARs configurable
through the Resizable BAR Capability Structure. This register is active only when the Resizable
BAR Capability is enabled for the Physical Function by setting the Enable Resizable BAR Capability
bit (bit 31) of the associated Physical Function BAR Configuration Register. When the Resizable BAR
Capability is not enabled, a read from this location returns all zeroes. When the Resizable BAR
Capability is enabled, all valid fields of this register can be modified from the local
management bus.

Offset = 188h + (n * 1000h); where n = 0h to 5h

Table 12-2613 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0188h + formula
Figure 12-1338 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_0 Register
31302928272625242322212019181716
R3
R-0h
1514131211109876543210
R3BARSRBARCR2BARI
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2614 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_0 Register Field Descriptions
BitFieldTypeResetDescription
31-13R3R0hReserved
12-8BARSR0hWhen the Resizable BAR Capability is enabled for the Physical Function, this field
controls the BAR aperture for the first BAR of the PF
[0 = 1M,
1 = 2M, ...
,
12 = 4G].
This
field can be modified independently for each PF from the local management bus.
7-5RBARCR0hSpecifies the number of BARs that can be configured through the Resizable BAR
Capability Structure for this PF.
This field can be modified independently for each PF from the
local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_COUNT values [where x is the function number]
for default values of each function in the reg_defaults.v files.
4-3R2R0hReserved
2-0BARIR0hSpecifies the index of the BAR controlled by this register.
This field can be modified
independently for each PF from the local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_CONTROL_REG0_BAR_INDEX values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.73 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_1 Register (Offset = 18Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CAP_1 is shown in Figure 12-1339 and described in Table 12-2616.

Return to the Summary Table.

This register advertises the available aperture settings of the first memory BAR of the
associated Physical Function. This register is active only when the Resizable BAR Capability
is enabled for the Physical Function by setting the Enable Resizable BAR Capability (bit 31) of
the associated Physical Function BAR Configuration Register 1. When the Resizable BAR Capability
is not enabled, a read from this location returns all zeros. When the Resizable BAR Capability
is enabled, any of the bits 4-22 can be modified from the local management bus.

Offset = 18Ch + (n * 1000h); where n = 0h to 5h

Table 12-2615 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 018Ch + formula
Figure 12-1339 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_1 Register
3130292827262524
R1
R-0h
2322212019181716
A512GA256GA128GA64GA32GA16GA8GA4G
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
A2GA1GA512MA256MA128MA64MA32MA16M
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
A8MA4MA2MA1MR0
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2616 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_1 Register Field Descriptions
BitFieldTypeResetDescription
31-24R1R0hReserved
23A512GR0hIndicates that the BAR aperture can be set to 512G.
22A256GR0hIndicates that the BAR aperture can be set to 256G.
21A128GR0hIndicates that the BAR aperture can be set to 128G.
20A64GR0hIndicates that the BAR aperture can be set to 64G.
19A32GR0hIndicates that the BAR aperture can be set to 32G.
18A16GR0hIndicates that the BAR aperture can be set to 16G.
17A8GR0hIndicates that the BAR aperture can be set to 8G.
16A4GR0hIndicates that the BAR aperture can be set to 4G.
15A2GR0hIndicates that the BAR aperture can be set to 2G.
14A1GR0hIndicates that the BAR aperture can be set to 1G.
13A512MR0hIndicates that the BAR aperture can be set to 512M.
12A256MR0hIndicates that the BAR aperture can be set to 256M.
11A128MR0hIndicates that the BAR aperture can be set to 128M.
10A64MR0hIndicates that the BAR aperture can be set to 64M.
9A32MR0hIndicates that the BAR aperture can be set to 32M.
8A16MR0hIndicates that the BAR aperture can be set to 16M.
7A8MR0hIndicates that the BAR aperture can be set to 8M.
6A4MR0hIndicates that the BAR aperture can be set to 4M.
5A2MR0hIndicates that the BAR aperture can be set to 2M.
4A1MR0hIndicates that the BAR aperture can be set to 1M.
3-0R0R0hReserved

3.5.1.74 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_1 Register (Offset = 190h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_1 is shown in Figure 12-1340 and described in Table 12-2618.

Return to the Summary Table.

This register controls the aperture setting of the first memory BAR of the associated
Physical Function, and also has a field that specifies the number of resizable BARs configurable
through the Resizable BAR Capability Structure. This register is active only when the Resizable
BAR Capability is enabled for the Physical Function by setting the Enable Resizable BAR Capability
bit (bit 31) of the associated Physical Function BAR Configuration Register. When the Resizable BAR
Capability is not enabled, a read from this location returns all zeroes. When the Resizable BAR
Capability is enabled, all valid fields of this register can be modified from the local
management bus.

Offset = 190h + (n * 1000h); where n = 0h to 5h

Table 12-2617 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0190h + formula
Figure 12-1340 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_1 Register
31302928272625242322212019181716
R3
R-0h
1514131211109876543210
R3BARSRBARCR2BARI
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2618 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
31-13R3R0hReserved
12-8BARSR0hWhen the Resizable BAR Capability is enabled for the Physical Function, this field
controls the BAR aperture for the first BAR of the PF
[0 = 1M,
1 = 2M, ...
,
12 = 4G].
This
field can be modified independently for each PF from the local management bus.
7-5RBARCR0hSpecifies the number of BARs that can be configured through the Resizable BAR
Capability Structure for this PF.
This field can be modified independently for each PF from the
local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_COUNT values [where x is the function number]
for default values of each function in the reg_defaults.v files.
4-3R2R0hReserved
2-0BARIR0hSpecifies the index of the BAR controlled by this register.
This field can be modified
independently for each PF from the local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_CONTROL_REG0_BAR_INDEX values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.75 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_2 Register (Offset = 194h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CAP_2 is shown in Figure 12-1341 and described in Table 12-2620.

Return to the Summary Table.

This register advertises the available aperture settings of the first memory BAR of the
associated Physical Function. This register is active only when the Resizable BAR Capability
is enabled for the Physical Function by setting the Enable Resizable BAR Capability (bit 31) of
the associated Physical Function BAR Configuration Register 1. When the Resizable BAR Capability
is not enabled, a read from this location returns all zeros. When the Resizable BAR Capability
is enabled, any of the bits 4-22 can be modified from the local management bus.

Offset = 194h + (n * 1000h); where n = 0h to 5h

Table 12-2619 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0194h + formula
Figure 12-1341 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_2 Register
3130292827262524
R1
R-0h
2322212019181716
A512GA256GA128GA64GA32GA16GA8GA4G
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
A2GA1GA512MA256MA128MA64MA32MA16M
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
A8MA4MA2MA1MR0
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2620 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_2 Register Field Descriptions
BitFieldTypeResetDescription
31-24R1R0hReserved
23A512GR0hIndicates that the BAR aperture can be set to 512G.
22A256GR0hIndicates that the BAR aperture can be set to 256G.
21A128GR0hIndicates that the BAR aperture can be set to 128G.
20A64GR0hIndicates that the BAR aperture can be set to 64G.
19A32GR0hIndicates that the BAR aperture can be set to 32G.
18A16GR0hIndicates that the BAR aperture can be set to 16G.
17A8GR0hIndicates that the BAR aperture can be set to 8G.
16A4GR0hIndicates that the BAR aperture can be set to 4G.
15A2GR0hIndicates that the BAR aperture can be set to 2G.
14A1GR0hIndicates that the BAR aperture can be set to 1G.
13A512MR0hIndicates that the BAR aperture can be set to 512M.
12A256MR0hIndicates that the BAR aperture can be set to 256M.
11A128MR0hIndicates that the BAR aperture can be set to 128M.
10A64MR0hIndicates that the BAR aperture can be set to 64M.
9A32MR0hIndicates that the BAR aperture can be set to 32M.
8A16MR0hIndicates that the BAR aperture can be set to 16M.
7A8MR0hIndicates that the BAR aperture can be set to 8M.
6A4MR0hIndicates that the BAR aperture can be set to 4M.
5A2MR0hIndicates that the BAR aperture can be set to 2M.
4A1MR0hIndicates that the BAR aperture can be set to 1M.
3-0R0R0hReserved

3.5.1.76 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_2 Register (Offset = 198h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_2 is shown in Figure 12-1342 and described in Table 12-2622.

Return to the Summary Table.

This register controls the aperture setting of the first memory BAR of the associated
Physical Function, and also has a field that specifies the number of resizable BARs configurable
through the Resizable BAR Capability Structure. This register is active only when the Resizable
BAR Capability is enabled for the Physical Function by setting the Enable Resizable BAR Capability
bit (bit 31) of the associated Physical Function BAR Configuration Register. When the Resizable BAR
Capability is not enabled, a read from this location returns all zeroes. When the Resizable BAR
Capability is enabled, all valid fields of this register can be modified from the local
management bus.

Offset = 198h + (n * 1000h); where n = 0h to 5h

Table 12-2621 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0198h + formula
Figure 12-1342 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_2 Register
31302928272625242322212019181716
R3
R-0h
1514131211109876543210
R3BARSRBARCR2BARI
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2622 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
31-13R3R0hReserved
12-8BARSR0hWhen the Resizable BAR Capability is enabled for the Physical Function, this field
controls the BAR aperture for the first BAR of the PF
[0 = 1M,
1 = 2M, ...
,
12 = 4G].
This
field can be modified independently for each PF from the local management bus.
7-5RBARCR0hSpecifies the number of BARs that can be configured through the Resizable BAR
Capability Structure for this PF.
This field can be modified independently for each PF from the
local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_COUNT values [where x is the function number]
for default values of each function in the reg_defaults.v files.
4-3R2R0hReserved
2-0BARIR0hSpecifies the index of the BAR controlled by this register.
This field can be modified
independently for each PF from the local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_CONTROL_REG0_BAR_INDEX values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.77 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_3 Register (Offset = 19Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CAP_3 is shown in Figure 12-1343 and described in Table 12-2624.

Return to the Summary Table.

This register advertises the available aperture settings of the first memory BAR of the
associated Physical Function. This register is active only when the Resizable BAR Capability
is enabled for the Physical Function by setting the Enable Resizable BAR Capability (bit 31) of
the associated Physical Function BAR Configuration Register 1. When the Resizable BAR Capability
is not enabled, a read from this location returns all zeros. When the Resizable BAR Capability
is enabled, any of the bits 4-22 can be modified from the local management bus.

Offset = 19Ch + (n * 1000h); where n = 0h to 5h

Table 12-2623 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 019Ch + formula
Figure 12-1343 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_3 Register
3130292827262524
R1
R-0h
2322212019181716
A512GA256GA128GA64GA32GA16GA8GA4G
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
A2GA1GA512MA256MA128MA64MA32MA16M
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
A8MA4MA2MA1MR0
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2624 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_3 Register Field Descriptions
BitFieldTypeResetDescription
31-24R1R0hReserved
23A512GR0hIndicates that the BAR aperture can be set to 512G.
22A256GR0hIndicates that the BAR aperture can be set to 256G.
21A128GR0hIndicates that the BAR aperture can be set to 128G.
20A64GR0hIndicates that the BAR aperture can be set to 64G.
19A32GR0hIndicates that the BAR aperture can be set to 32G.
18A16GR0hIndicates that the BAR aperture can be set to 16G.
17A8GR0hIndicates that the BAR aperture can be set to 8G.
16A4GR0hIndicates that the BAR aperture can be set to 4G.
15A2GR0hIndicates that the BAR aperture can be set to 2G.
14A1GR0hIndicates that the BAR aperture can be set to 1G.
13A512MR0hIndicates that the BAR aperture can be set to 512M.
12A256MR0hIndicates that the BAR aperture can be set to 256M.
11A128MR0hIndicates that the BAR aperture can be set to 128M.
10A64MR0hIndicates that the BAR aperture can be set to 64M.
9A32MR0hIndicates that the BAR aperture can be set to 32M.
8A16MR0hIndicates that the BAR aperture can be set to 16M.
7A8MR0hIndicates that the BAR aperture can be set to 8M.
6A4MR0hIndicates that the BAR aperture can be set to 4M.
5A2MR0hIndicates that the BAR aperture can be set to 2M.
4A1MR0hIndicates that the BAR aperture can be set to 1M.
3-0R0R0hReserved

3.5.1.78 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_3 Register (Offset = 1A0h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_3 is shown in Figure 12-1344 and described in Table 12-2626.

Return to the Summary Table.

This register controls the aperture setting of the first memory BAR of the associated
Physical Function, and also has a field that specifies the number of resizable BARs configurable
through the Resizable BAR Capability Structure. This register is active only when the Resizable
BAR Capability is enabled for the Physical Function by setting the Enable Resizable BAR Capability
bit (bit 31) of the associated Physical Function BAR Configuration Register. When the Resizable BAR
Capability is not enabled, a read from this location returns all zeroes. When the Resizable BAR
Capability is enabled, all valid fields of this register can be modified from the local
management bus.

Offset = 1A0h + (n * 1000h); where n = 0h to 5h

Table 12-2625 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01A0h + formula
Figure 12-1344 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_3 Register
31302928272625242322212019181716
R3
R-0h
1514131211109876543210
R3BARSRBARCR2BARI
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2626 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
31-13R3R0hReserved
12-8BARSR0hWhen the Resizable BAR Capability is enabled for the Physical Function, this field
controls the BAR aperture for the first BAR of the PF
[0 = 1M,
1 = 2M, ...
,
12 = 4G].
This
field can be modified independently for each PF from the local management bus.
7-5RBARCR0hSpecifies the number of BARs that can be configured through the Resizable BAR
Capability Structure for this PF.
This field can be modified independently for each PF from the
local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_COUNT values [where x is the function number]
for default values of each function in the reg_defaults.v files.
4-3R2R0hReserved
2-0BARIR0hSpecifies the index of the BAR controlled by this register.
This field can be modified
independently for each PF from the local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_CONTROL_REG0_BAR_INDEX values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.79 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_4 Register (Offset = 1A4h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CAP_4 is shown in Figure 12-1345 and described in Table 12-2628.

Return to the Summary Table.

This register advertises the available aperture settings of the first memory BAR of the
associated Physical Function. This register is active only when the Resizable BAR Capability
is enabled for the Physical Function by setting the Enable Resizable BAR Capability (bit 31) of
the associated Physical Function BAR Configuration Register 1. When the Resizable BAR Capability
is not enabled, a read from this location returns all zeros. When the Resizable BAR Capability
is enabled, any of the bits 4-22 can be modified from the local management bus.

Offset = 1A4h + (n * 1000h); where n = 0h to 5h

Table 12-2627 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_4 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01A4h + formula
Figure 12-1345 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_4 Register
3130292827262524
R1
R-0h
2322212019181716
A512GA256GA128GA64GA32GA16GA8GA4G
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
A2GA1GA512MA256MA128MA64MA32MA16M
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
A8MA4MA2MA1MR0
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2628 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_4 Register Field Descriptions
BitFieldTypeResetDescription
31-24R1R0hReserved
23A512GR0hIndicates that the BAR aperture can be set to 512G.
22A256GR0hIndicates that the BAR aperture can be set to 256G.
21A128GR0hIndicates that the BAR aperture can be set to 128G.
20A64GR0hIndicates that the BAR aperture can be set to 64G.
19A32GR0hIndicates that the BAR aperture can be set to 32G.
18A16GR0hIndicates that the BAR aperture can be set to 16G.
17A8GR0hIndicates that the BAR aperture can be set to 8G.
16A4GR0hIndicates that the BAR aperture can be set to 4G.
15A2GR0hIndicates that the BAR aperture can be set to 2G.
14A1GR0hIndicates that the BAR aperture can be set to 1G.
13A512MR0hIndicates that the BAR aperture can be set to 512M.
12A256MR0hIndicates that the BAR aperture can be set to 256M.
11A128MR0hIndicates that the BAR aperture can be set to 128M.
10A64MR0hIndicates that the BAR aperture can be set to 64M.
9A32MR0hIndicates that the BAR aperture can be set to 32M.
8A16MR0hIndicates that the BAR aperture can be set to 16M.
7A8MR0hIndicates that the BAR aperture can be set to 8M.
6A4MR0hIndicates that the BAR aperture can be set to 4M.
5A2MR0hIndicates that the BAR aperture can be set to 2M.
4A1MR0hIndicates that the BAR aperture can be set to 1M.
3-0R0R0hReserved

3.5.1.80 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_4 Register (Offset = 1A8h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_4 is shown in Figure 12-1346 and described in Table 12-2630.

Return to the Summary Table.

This register controls the aperture setting of the first memory BAR of the associated
Physical Function, and also has a field that specifies the number of resizable BARs configurable
through the Resizable BAR Capability Structure. This register is active only when the Resizable
BAR Capability is enabled for the Physical Function by setting the Enable Resizable BAR Capability
bit (bit 31) of the associated Physical Function BAR Configuration Register. When the Resizable BAR
Capability is not enabled, a read from this location returns all zeroes. When the Resizable BAR
Capability is enabled, all valid fields of this register can be modified from the local
management bus.

Offset = 1A8h + (n * 1000h); where n = 0h to 5h

Table 12-2629 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_4 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01A8h + formula
Figure 12-1346 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_4 Register
31302928272625242322212019181716
R3
R-0h
1514131211109876543210
R3BARSRBARCR2BARI
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2630 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_4 Register Field Descriptions
BitFieldTypeResetDescription
31-13R3R0hReserved
12-8BARSR0hWhen the Resizable BAR Capability is enabled for the Physical Function, this field
controls the BAR aperture for the first BAR of the PF
[0 = 1M,
1 = 2M, ...
,
12 = 4G].
This
field can be modified independently for each PF from the local management bus.
7-5RBARCR0hSpecifies the number of BARs that can be configured through the Resizable BAR
Capability Structure for this PF.
This field can be modified independently for each PF from the
local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_COUNT values [where x is the function number]
for default values of each function in the reg_defaults.v files.
4-3R2R0hReserved
2-0BARIR0hSpecifies the index of the BAR controlled by this register.
This field can be modified
independently for each PF from the local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_CONTROL_REG0_BAR_INDEX values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.81 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_5 Register (Offset = 1ACh + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CAP_5 is shown in Figure 12-1347 and described in Table 12-2632.

Return to the Summary Table.

This register advertises the available aperture settings of the first memory BAR of the
associated Physical Function. This register is active only when the Resizable BAR Capability
is enabled for the Physical Function by setting the Enable Resizable BAR Capability (bit 31) of
the associated Physical Function BAR Configuration Register 1. When the Resizable BAR Capability
is not enabled, a read from this location returns all zeros. When the Resizable BAR Capability
is enabled, any of the bits 4-22 can be modified from the local management bus.

Offset = 1ACh + (n * 1000h); where n = 0h to 5h

Table 12-2631 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_5 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01ACh + formula
Figure 12-1347 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_5 Register
3130292827262524
R1
R-0h
2322212019181716
A512GA256GA128GA64GA32GA16GA8GA4G
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
A2GA1GA512MA256MA128MA64MA32MA16M
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
A8MA4MA2MA1MR0
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2632 PCIE_CORE_PFn_I_RESIZE_BAR_CAP_5 Register Field Descriptions
BitFieldTypeResetDescription
31-24R1R0hReserved
23A512GR0hIndicates that the BAR aperture can be set to 512G.
22A256GR0hIndicates that the BAR aperture can be set to 256G.
21A128GR0hIndicates that the BAR aperture can be set to 128G.
20A64GR0hIndicates that the BAR aperture can be set to 64G.
19A32GR0hIndicates that the BAR aperture can be set to 32G.
18A16GR0hIndicates that the BAR aperture can be set to 16G.
17A8GR0hIndicates that the BAR aperture can be set to 8G.
16A4GR0hIndicates that the BAR aperture can be set to 4G.
15A2GR0hIndicates that the BAR aperture can be set to 2G.
14A1GR0hIndicates that the BAR aperture can be set to 1G.
13A512MR0hIndicates that the BAR aperture can be set to 512M.
12A256MR0hIndicates that the BAR aperture can be set to 256M.
11A128MR0hIndicates that the BAR aperture can be set to 128M.
10A64MR0hIndicates that the BAR aperture can be set to 64M.
9A32MR0hIndicates that the BAR aperture can be set to 32M.
8A16MR0hIndicates that the BAR aperture can be set to 16M.
7A8MR0hIndicates that the BAR aperture can be set to 8M.
6A4MR0hIndicates that the BAR aperture can be set to 4M.
5A2MR0hIndicates that the BAR aperture can be set to 2M.
4A1MR0hIndicates that the BAR aperture can be set to 1M.
3-0R0R0hReserved

3.5.1.82 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_5 Register (Offset = 1B0h + formula) [reset = 0h]

PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_5 is shown in Figure 12-1348 and described in Table 12-2634.

Return to the Summary Table.

This register controls the aperture setting of the first memory BAR of the associated
Physical Function, and also has a field that specifies the number of resizable BARs configurable
through the Resizable BAR Capability Structure. This register is active only when the Resizable
BAR Capability is enabled for the Physical Function by setting the Enable Resizable BAR Capability
bit (bit 31) of the associated Physical Function BAR Configuration Register. When the Resizable BAR
Capability is not enabled, a read from this location returns all zeroes. When the Resizable BAR
Capability is enabled, all valid fields of this register can be modified from the local
management bus.

Offset = 1B0h + (n * 1000h); where n = 0h to 5h

Table 12-2633 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_5 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01B0h + formula
Figure 12-1348 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_5 Register
31302928272625242322212019181716
R3
R-0h
1514131211109876543210
R3BARSRBARCR2BARI
R-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2634 PCIE_CORE_PFn_I_RESIZE_BAR_CTRL_5 Register Field Descriptions
BitFieldTypeResetDescription
31-13R3R0hReserved
12-8BARSR0hWhen the Resizable BAR Capability is enabled for the Physical Function, this field
controls the BAR aperture for the first BAR of the PF
[0 = 1M,
1 = 2M, ...
,
12 = 4G].
This
field can be modified independently for each PF from the local management bus.
7-5RBARCR0hSpecifies the number of BARs that can be configured through the Resizable BAR
Capability Structure for this PF.
This field can be modified independently for each PF from the
local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_COUNT values [where x is the function number]
for default values of each function in the reg_defaults.v files.
4-3R2R0hReserved
2-0BARIR0hSpecifies the index of the BAR controlled by this register.
This field can be modified
independently for each PF from the local management bus.
Please see the define den_db_Fx_RESIZABLE_BAR_CONTROL_REG0_BAR_INDEX values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.83 PCIE_CORE_PF0_I_LTR_EXT_CAP_HDR Register (Offset = 1B8h) [reset = 1C010018h]

PCIE_CORE_PF0_I_LTR_EXT_CAP_HDR is shown in Figure 12-1349 and described in Table 12-2636.

Return to the Summary Table.

This register contains the PCI Express Extended Capability ID for the Latency Tolerance
Reporting (LTR) Capability, its capability version, and the pointer to the next capability
structure. This register is implemented only for Physical Function 0. A read from this address
of other Physical Functions configuration space returns all zeroes.

Table 12-2635 PCIE_CORE_PF0_I_LTR_EXT_CAP_HDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01B8h
Figure 12-1349 PCIE_CORE_PF0_I_LTR_EXT_CAP_HDR Register
313029282726252423222120191817161514131211109876543210
NCOCVPECID
R/W-1C0hR/W-1hR-18h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2636 PCIE_CORE_PF0_I_LTR_EXT_CAP_HDR Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W1C0hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified from the local management bus.
15-0PECIDR18hThis field is hardwired to the Capability ID assigned by PCI SIG to the Latency
Tolerance Reporting Capability [0018 hex].

3.5.1.84 PCIE_CORE_PF0_I_LTR_SNOOP_LAT Register (Offset = 1BCh) [reset = 0h]

PCIE_CORE_PF0_I_LTR_SNOOP_LAT is shown in Figure 12-1350 and described in Table 12-2638.

Return to the Summary Table.

This register contains the maximum snoop latency and the maximum no-snoop latency that
the device is allowed to request in an LTR message it originates.

Table 12-2637 PCIE_CORE_PF0_I_LTR_SNOOP_LAT Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01BCh
Figure 12-1350 PCIE_CORE_PF0_I_LTR_SNOOP_LAT Register
31302928272625242322212019181716
R1MNSLSMNSL
R-0hR/W-0hR/W-0h
1514131211109876543210
R0MSLSMSL
R-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2638 PCIE_CORE_PF0_I_LTR_SNOOP_LAT Register Field Descriptions
BitFieldTypeResetDescription
31-29R1R0hReserved
28-26MNSLSR/W0hSpecifies the scale value for the Max No-Snoop Latency.
When the setting of this field
is non-zero, the actual snoop latency is determined by multiplying the Max No-Snoop Latency by
the following scale factors:
001: 32 ns,
010: 1024 ns,
011: 32,768 ns,
100: 1,047,576 ns,
101:
33,554,432 ns,
110-
111: Reserved
25-16MNSLR/W0hWhen multiplied by the value of the Max No-Snoop Latency Scale, this field defines the
maximum no-snoop value the device is permitted to request in an LTR message.
This field can be
written independently for each Physical Function from the local management bus.
15-13R0R0hReserved
12-10MSLSR/W0hSpecifies the scale value for the Max Snoop Latency.
When the setting of this field is
non-zero, the actual snoop latency is determined by multiplying the Max Snoop Latency by the
following scale factors:
001: 32 ns,
010: 1024 ns,
011: 32,768 ns,
100: 1,047,576 ns,
101:
33,554,432 ns,
110-
111: Reserved
9-0MSLR/W0hWhen multiplied by the value of the Max Snoop Latency Scale, this field defines the
maximum snoop value the device is permitted to request in an LTR message.
This field can be
written independently for each Physical Function from the local management bus.

3.5.1.85 PCIE_CORE_PFn_I_DPA_EXT_CAP_HEADER_REG Register (Offset = 1C0h + formula) [reset = 20010016h]

PCIE_CORE_PFn_I_DPA_EXT_CAP_HEADER_REG is shown in Figure 12-1351 and described in Table 12-2640.

Return to the Summary Table.

This location contains the PCI Express Extended Capability ID for DPA Capability and the
offset to the next capability block.

Offset = 1C0h + (n * 1000h); where n = 0h to 5h

Table 12-2639 PCIE_CORE_PFn_I_DPA_EXT_CAP_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01C0h + formula
Figure 12-1351 PCIE_CORE_PFn_I_DPA_EXT_CAP_HEADER_REG Register
313029282726252423222120191817161514131211109876543210
NCOCVPECID
R/W-200hR/W-1hR-16h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2640 PCIE_CORE_PFn_I_DPA_EXT_CAP_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W200hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified from the local management bus.
15-0PECIDR16hThis field is hardwired to the Capability ID assigned by PCI SIG to the Dynamic Power
Allocation Reporting Capability

3.5.1.86 PCIE_CORE_PFn_I_DPA_CAP_REG Register (Offset = 1C4h + formula) [reset = 08100007h]

PCIE_CORE_PFn_I_DPA_CAP_REG is shown in Figure 12-1352 and described in Table 12-2642.

Return to the Summary Table.

This register contains the DPA capability parameters for the associated Function.

Offset = 1C4h + (n * 1000h); where n = 0h to 5h

Table 12-2641 PCIE_CORE_PFn_I_DPA_CAP_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01C4h + formula
Figure 12-1352 PCIE_CORE_PFn_I_DPA_CAP_REG Register
31302928272625242322212019181716
TLV1TLV0
R/W-8hR/W-10h
1514131211109876543210
R2PASR1TLUR0MNS
R-0hR/W-0hR-0hR/W-0hR-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2642 PCIE_CORE_PFn_I_DPA_CAP_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24TLV1R/W8hSpecifies the second of the two transition latency values for the substates.
The unit
of latency is specified by the Transition Latency Unit field of this register.
Please see the define den_db_Fx_DPA_CAPABILITY_REG_TRANSITION_VALUE1 values [where x is the function number]
for default values of each function in the reg_defaults.v files.
23-16TLV0R/W10hSpecifies the transition latency for the substate.
Each of the 32 substates may
specify one of the two transition latency values.
This field contains the first of the two
latency values.
The unit of latency is specified by the Transition Latency Unit field of this
register.
Please see the define den_db_Fx_DPA_CAPABILITY_REG_TRANSITION_VALUE0 values [where x is the function number]
for default values of each function in the reg_defaults.v files.
15-14R2R0hReserved
13-12PASR/W0hThis is the scale used to compute the actual power from the values specified in the
Dynamic Power Allocation Array Registers
0 - 7.
The actual power in Watts is obtained by
multiplying the value in the Dynamic Power Allocation Array Register by this scale factor
[00 =
10x,
01 = 1x,
10 = 0.1x,
11 = 0.01x].
Please see the define den_db_Fx_DPA_CAPABILITY_REG_POWER_ALLOCATION_SCALE values [where x is the function number]
for default values of each function in the reg_defaults.v files.
11-10R1R0hReserved
9-8TLUR/W0hThis is the unit of the transition latencies specified in the Transition Latency Value
0 and Transition Latency Value 1 fields of this register [
00 = 1 ms,
01 = 10 ms,
10 = 100 ms,

11 = reserved].
Please see the define den_db_Fx_DPA_CAPABILITY_REG_TRANSITION_LATENCY_UNIT values [where x is the function number]
for default values of each function in the reg_defaults.v files.
7-5R0R0hReserved
4-0MNSR/W7hMaximum number of DPA substates supported by the Function [the value in this field is
the number of substates minus 1].
Please see the define den_db_Fx_DPA_CAPABILITY_REG_SUBSTATE_MAX values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.87 PCIE_CORE_PFn_I_DPA_LAT_INDICATOR_REG Register (Offset = 1C8h + formula) [reset = 0h]

PCIE_CORE_PFn_I_DPA_LAT_INDICATOR_REG is shown in Figure 12-1353 and described in Table 12-2644.

Return to the Summary Table.

This location contains Transition Latency Indicator bits for the DPA substates.

Offset = 1C8h + (n * 1000h); where n = 0h to 5h

Table 12-2643 PCIE_CORE_PFn_I_DPA_LAT_INDICATOR_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01C8h + formula
Figure 12-1353 PCIE_CORE_PFn_I_DPA_LAT_INDICATOR_REG Register
313029282726252423222120191817161514131211109876543210
TLIN
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2644 PCIE_CORE_PFn_I_DPA_LAT_INDICATOR_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0TLINR/W0hBit i of this register indicates the choice of the transition latency value for
substate i.
A setting of 0 indicates that Transition Latency Value 0 from the DPA Capability
Register applies to this substate
a setting of 1 indicates that Transition Latency Value 1
applies.
Please see the define den_db_Fx_DPA_TRANSITION_LATENCY values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.88 PCIE_CORE_PFn_I_DPA_CTRL_STATUS_REG Register (Offset = 1CCh + formula) [reset = 100h]

PCIE_CORE_PFn_I_DPA_CTRL_STATUS_REG is shown in Figure 12-1354 and described in Table 12-2646.

Return to the Summary Table.

This location contains the DPA Control Register and the DPA Status Register.

Offset = 1CCh + (n * 1000h); where n = 0h to 5h

Table 12-2645 PCIE_CORE_PFn_I_DPA_CTRL_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01CCh + formula
Figure 12-1354 PCIE_CORE_PFn_I_DPA_CTRL_STATUS_REG Register
31302928272625242322212019181716
R5SC
R-0hR/W-0h
1514131211109876543210
R4SCER3SS
R-0hR/W-1hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2646 PCIE_CORE_PFn_I_DPA_CTRL_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-21R5R0hReserved
20-16SCR/W0hThis field is used to initiate a transition of the Function's DPA to a new substate.
To initiate the transition, software must write the desired substate value into this field and
wait for the transition latency of the substate for the Function to complete the transition.
This field can also be written from the local management bus.
All substate transitions are
disabled when the Substate Control Enabled bit is 0.
The Controller generates a one-cycle pulse on
the output DPA_INTERRUPT when the value if this field is changed [bit 0 is for PF 0 and so on]
This interrupt informs the client of the request from software to change the DPA
substate.
In response, the client must read the Substate Control field from this register to
determine the new substate, and perform the actions necessary to effect the substate change.
On completion of the substate change, the client must update the Substate Status field to
reflect the new substate the function is in.
15-9R4R0hReserved
8SCER/W1hThis bit enables the Substate Control field.
This bit is initialized to 1 by the
hardware on a power-on reset or a Function-Level Reset.
Software may clear this bit by writing a 1
to this bit position, but cannot set this bit directly through a configuration write.
Clearing this bit disables the Substate Control field, thus preventing further substate
transitions for this Function.
This bit can be set to 0 or 1 through the local management
bus, by writing a 0 or 1, respectively.
7-5R3R0hReserved
4-0SSR/W0hThis field provides the current DPA substate of this Function.
This field is
writable from the local management bus, and must be updated by the local software running on
the EndPoint upon completion of a DPA transition to a new substate.

3.5.1.89 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG0 Register (Offset = 1D0h + formula) [reset = 03020100h]

PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG0 is shown in Figure 12-1355 and described in Table 12-2648.

Return to the Summary Table.

This is a register in an array of 2registers that contain the power allocations
for the DPA substates. Each location contains power allocation values for four substates, 8 bits
per substate. The value in each 8-bit field, when multiplied by the Power Allocation Scale
programmed in the DPA Capability Register, provides the power associated with the corresponding
substate in Watts.

Offset = 1D0h + (n * 1000h); where n = 0h to 5h

Table 12-2647 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01D0h + formula
Figure 12-1355 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG0 Register
313029282726252423222120191817161514131211109876543210
SPA3_0SPA2_0SPA1_0SPA0_0
R/W-3hR/W-2hR/W-1hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2648 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-24SPA3_0R/W3hThis field contains the power allocation for the DPA substate #3 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.
23-16SPA2_0R/W2hThis field contains the power allocation for the DPA substate #2 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.
15-8SPA1_0R/W1hThis field contains the power allocation for the DPA substate #1 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.
7-0SPA0_0R/W0hThis field contains the power allocation for the DPA substate #0 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.

3.5.1.90 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG1 Register (Offset = 1D4h + formula) [reset = 07060504h]

PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG1 is shown in Figure 12-1356 and described in Table 12-2650.

Return to the Summary Table.

This is a register in an array of 2registers that contain the power allocations
for the DPA substates. Each location contains power allocation values for four substates, 8 bits
per substate. The value in each 8-bit field, when multiplied by the Power Allocation Scale
programmed in the DPA Capability Register, provides the power associated with the corresponding
substate in Watts.

Offset = 1D4h + (n * 1000h); where n = 0h to 5h

Table 12-2649 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01D4h + formula
Figure 12-1356 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG1 Register
313029282726252423222120191817161514131211109876543210
SPA3_1SPA2_1SPA1_1SPA0_1
R/W-7hR/W-6hR/W-5hR/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2650 PCIE_CORE_PFn_I_DPA_POWER_ALLOC_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-24SPA3_1R/W7hThis field contains the power allocation for the DPA substate #7 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.
23-16SPA2_1R/W6hThis field contains the power allocation for the DPA substate #6 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.
15-8SPA1_1R/W5hThis field contains the power allocation for the DPA substate #5 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.
7-0SPA0_1R/W4hThis field contains the power allocation for the DPA substate #4 covered by this
register.
This value, when multiplied by the Power Allocation Scale programmed in the DPA
Capability Register, provides the power associated with the corresponding substate in Watts.

3.5.1.91 PCIE_CORE_PFn_RSVD_07C_07F Register (Offset = 1D8h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_07C_07F is shown in Figure 12-1357 and described in Table 12-2652.

Return to the Summary Table.

Reserved

Offset = 1D8h + (n * 1000h); where n = 0h to 5h

Table 12-2651 PCIE_CORE_PFn_RSVD_07C_07F Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 01D8h + formula
Figure 12-1357 PCIE_CORE_PFn_RSVD_07C_07F Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2652 PCIE_CORE_PFn_RSVD_07C_07F Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.92 PCIE_CORE_PFn_I_SRIOV_EXT_CAP_HEADER_REG Register (Offset = 200h + formula) [reset = 30010010h]

PCIE_CORE_PFn_I_SRIOV_EXT_CAP_HEADER_REG is shown in Figure 12-1358 and described in Table 12-2654.

Return to the Summary Table.

This location contains the PCI Express Extended Capability ID for SR-IOV and the offset
to the next capability block.

Offset = 200h + (n * 1000h); where n = 0h to 5h

Table 12-2653 PCIE_CORE_PFn_I_SRIOV_EXT_CAP_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0200h + formula
Figure 12-1358 PCIE_CORE_PFn_I_SRIOV_EXT_CAP_HEADER_REG Register
313029282726252423222120191817161514131211109876543210
NCOCVPECID
R/W-300hR/W-1hR-10h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2654 PCIE_CORE_PFn_I_SRIOV_EXT_CAP_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W300hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG-assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified independently for each Function from the
local management bus.
15-0PECIDR10hThis field is hardwired to the Capability ID assigned by PCI-SIG to the SR-IOV
Extended Capability Structure [0010 hex].

3.5.1.93 PCIE_CORE_PFn_I_SRIOV_CAP_REG Register (Offset = 204h + formula) [reset = 2h]

PCIE_CORE_PFn_I_SRIOV_CAP_REG is shown in Figure 12-1359 and described in Table 12-2656.

Return to the Summary Table.

This register defines various capabilities of the SR-IOV implementation.

Offset = 204h + (n * 1000h); where n = 0h to 5h

Table 12-2655 PCIE_CORE_PFn_I_SRIOV_CAP_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0204h + formula
Figure 12-1359 PCIE_CORE_PFn_I_SRIOV_CAP_REG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDVFT10RSACHPVFMC
R-0hR-0hR/W-1hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2656 PCIE_CORE_PFn_I_SRIOV_CAP_REG Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2VFT10RSR0hIf set all VFs associated with this PF supports
1-bit requester capability
otherwise, the VF does not.
This bit can be disabled using local management register.
1ACHPR/W1hA 1 in this bit position indicates that the ARI Capable Hierarchy bit in the SR-IOV
Control Register is preserved across certain power state transitions [see the PCI-SIG Single
Root IO Virtualization and Sharing Specifications, Version 1.1, Section 3.3.3.5 for details].
This bit is set to 1 by default, but can be modified from the local management bus.
0VFMCR0hSet when the Controller supports VF migration.
Hardwired to 0.

3.5.1.94 PCIE_CORE_PFn_I_SRIOV_CTRL_STATUS_REG Register (Offset = 208h + formula) [reset = 0h]

PCIE_CORE_PFn_I_SRIOV_CTRL_STATUS_REG is shown in Figure 12-1360 and described in Table 12-2658.

Return to the Summary Table.

This location contains the SR-IOV Control Register and the SR-IOV Status Register.

Offset = 208h + (n * 1000h); where n = 0h to 5h

Table 12-2657 PCIE_CORE_PFn_I_SRIOV_CTRL_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0208h + formula
Figure 12-1360 PCIE_CORE_PFn_I_SRIOV_CTRL_STATUS_REG Register
3130292827262524
SSR
R-0h
2322212019181716
SSR
R-0h
15141312111098
R15
R-0h
76543210
R15T10REARIEVFMSEVFMIEVFMEVFE
R-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2658 PCIE_CORE_PFn_I_SRIOV_CTRL_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16SSRR0hNot implemented.
15-6R15R0hReserved
5T10RER0h10bit TAGs generation are not supported in this configuration.
4ARIER/W0hThis bit enables the ARI mode for Virtual Functions.

ARI Capable Hierarchy is only present in the lowest numbered PF which is enabled [for example PF0] and affects all PFs of the Device.
ARI Capable Hierarchy is Read Only Zero in other PFs of a Device.
3VFMSER/W0hThis bit must be set to allow access to the memory space of the VFs associated with
this PF.
2VFMIER/W0hNot supported.
Hardwired to 0
1VFMER/W0hNot supported.
Hardwired to 0
0VFER/W0hThis bit must be set to enable the VFs associated with this PF.

3.5.1.95 PCIE_CORE_PFn_I_INITIAL_TOTAL_VFS_REG Register (Offset = 20Ch + formula) [reset = X]

PCIE_CORE_PFn_I_INITIAL_TOTAL_VFS_REG is shown in Figure 12-1361 and described in Table 12-2660.

Return to the Summary Table.

This location contains registers that specify the initial and the total number Virtual
Functions (VFs) in the device.

Offset = 20Ch + (n * 1000h); where n = 0h to 5h

Table 12-2659 PCIE_CORE_PFn_I_INITIAL_TOTAL_VFS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 020Ch + formula
Figure 12-1361 PCIE_CORE_PFn_I_INITIAL_TOTAL_VFS_REG Register
313029282726252423222120191817161514131211109876543210
RESERVEDTVFRESERVEDIVF
R/W-XR/W-4hR/W-XR/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2660 PCIE_CORE_PFn_I_INITIAL_TOTAL_VFS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR/WX
20-16TVFR/W4hThis field contains the total number of VFs per PF.
Its default setting is identical
to that of InitialVFs.
This field can be
modified using local management registers.
15-5RESERVEDR/WX
4-0IVFR/W4hThis field contains the initial number of VFs configured for each PF.
This field can be
modified using local management registers.
Please see the define den_db_PFx_TOTAL_VF_COUNT values [where x is the function number]
for default values of each function in the reg_defaults.v files.

3.5.1.96 PCIE_CORE_PFn_I_FUNC_DEP_LINK_NUMVFS_REG Register (Offset = 210h + formula) [reset = X]

PCIE_CORE_PFn_I_FUNC_DEP_LINK_NUMVFS_REG is shown in Figure 12-1362 and described in Table 12-2662.

Return to the Summary Table.

This location contains the Function Dependency Link that defines VF dependencies, and
the NumVFs register that stores the number of VFs configured.

Offset = 210h + (n * 1000h); where n = 0h to 5h

Table 12-2661 PCIE_CORE_PFn_I_FUNC_DEP_LINK_NUMVFS_REG Instances
Figure 12-1362 PCIE_CORE_PFn_I_FUNC_DEP_LINK_NUMVFS_REG Register
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2662 PCIE_CORE_PFn_I_FUNC_DEP_LINK_NUMVFS_REG Register Field Descriptions

3.5.1.97 PCIE_CORE_PFn_I_VF_OFFSET_STRIDE_REG Register (Offset = 214h + formula) [reset = 00010006h]

PCIE_CORE_PFn_I_VF_OFFSET_STRIDE_REG is shown in Figure 12-1363 and described in Table 12-2664.

Return to the Summary Table.

Specifies the offset and stride values for VF address assignment.

Offset = 214h + (n * 1000h); where n = 0h to 5h

Table 12-2663 PCIE_CORE_PFn_I_VF_OFFSET_STRIDE_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0214h + formula
Figure 12-1363 PCIE_CORE_PFn_I_VF_OFFSET_STRIDE_REG Register
313029282726252423222120191817161514131211109876543210
VFSFVFO
R-1hR/W-6h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2664 PCIE_CORE_PFn_I_VF_OFFSET_STRIDE_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16VFSR1hStride value used to assign RIDs for VFs.
The stride value is hardwired to 1 for all
Physical Functions.
15-0FVFOR/W6hOffset of First VF relative to its PF.
Modifying this field is not supported.

3.5.1.98 PCIE_CORE_PFn_I_VF_DEVICE_ID_REG Register (Offset = 218h + formula) [reset = 01000000h]

PCIE_CORE_PFn_I_VF_DEVICE_ID_REG is shown in Figure 12-1364 and described in Table 12-2666.

Return to the Summary Table.

This register specifies the VF device id for the device.

Offset = 218h + (n * 1000h); where n = 0h to 5h

Table 12-2665 PCIE_CORE_PFn_I_VF_DEVICE_ID_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0218h + formula
Figure 12-1364 PCIE_CORE_PFn_I_VF_DEVICE_ID_REG Register
313029282726252423222120191817161514131211109876543210
VFDIR2
R/W-100hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2666 PCIE_CORE_PFn_I_VF_DEVICE_ID_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16VFDIR/W100hVF device id assigned to the device.
Its default value is specified in reg_defaults.h,
but can be re-written independently for each PF from the local management bus.
15-0R2R0hReserved

3.5.1.99 PCIE_CORE_PFn_I_SUPPORTED_PAGE_SIZE_REG Register (Offset = 21Ch + formula) [reset = 553h]

PCIE_CORE_PFn_I_SUPPORTED_PAGE_SIZE_REG is shown in Figure 12-1365 and described in Table 12-2668.

Return to the Summary Table.

This register specifies all the page sizes supported by the device.

Offset = 21Ch + (n * 1000h); where n = 0h to 5h

Table 12-2667 PCIE_CORE_PFn_I_SUPPORTED_PAGE_SIZE_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 021Ch + formula
Figure 12-1365 PCIE_CORE_PFn_I_SUPPORTED_PAGE_SIZE_REG Register
313029282726252423222120191817161514131211109876543210
R0PS
R-0hR/W-553h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2668 PCIE_CORE_PFn_I_SUPPORTED_PAGE_SIZE_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R0R0hReserved
15-0PSR/W553hPage sizes supported by the device [one bit for each page size].
The Controller implements
only bits
15:0 of this register.
The default value of this field is specified in
reg_defaults.h, but can be re-written independently for each PF from the local management
bus.

3.5.1.100 PCIE_CORE_PFn_I_SYSTEM_PAGE_SIZE_REG Register (Offset = 220h + formula) [reset = 1h]

PCIE_CORE_PFn_I_SYSTEM_PAGE_SIZE_REG is shown in Figure 12-1366 and described in Table 12-2670.

Return to the Summary Table.

This register identifies the page size currently used by the system.

Offset = 220h + (n * 1000h); where n = 0h to 5h

Table 12-2669 PCIE_CORE_PFn_I_SYSTEM_PAGE_SIZE_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0220h + formula
Figure 12-1366 PCIE_CORE_PFn_I_SYSTEM_PAGE_SIZE_REG Register
313029282726252423222120191817161514131211109876543210
R0SPS
R-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2670 PCIE_CORE_PFn_I_SYSTEM_PAGE_SIZE_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R0R0hReserved
15-0SPSR/W1hThis field must be programmed by software to the current page size in use.
The
Controller
implements only bits
15:0 of this register.
This field can also be written from the local
management bus.

3.5.1.101 PCIE_CORE_PFn_I_VF_BAR_0_REG Register (Offset = 224h + formula) [reset = 4h]

PCIE_CORE_PFn_I_VF_BAR_0_REG is shown in Figure 12-1367 and described in Table 12-2672.

Return to the Summary Table.

This is part of the set of six Virtual Function Base Address Registers defined
by the SR-IOV Specifications. These registers are used to define address ranges for memory
accesses to the Endpoint device. This register may be used to define a range of 32-bit addresses,
or paired with the next adjacent register to define a 64-bit address range.
During the initial configuration of the device, the configuration program determines the size of
the address range defined by the BAR by writing a pattern of all 1's into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned value.
A value of 0 is returned by the Controller if this BAR is not configured. Otherwise, the number of 1's returned
is based on the length of the BAR.

Offset = 224h + (n * 1000h); where n = 0h to 5h

Table 12-2671 PCIE_CORE_PFn_I_VF_BAR_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0224h + formula
Figure 12-1367 PCIE_CORE_PFn_I_VF_BAR_0_REG Register
31302928272625242322212019181716
BAMRWBAMR0
R/W-0hR-0h
1514131211109876543210
BAMR0R8P0S0R7MSI
R-0hR-0hR-0hR-1hR-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2672 PCIE_CORE_PFn_I_VF_BAR_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-22BAMRWR/W0hThis field defines the base address of the memory address range.
The number of implemented
bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated
Physical Function.
21-8BAMR0R0hThis field defines the base address of the memory address range.
The number of implemented
bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated
Physical Function.
All other bits are not writeable, and are read as 0's.
7-4R8R0hThese bits are hardwired to 0
3P0R0hWhen the BAR is used to define a memory address range, this field declares whether
data from the address range is prefetchable
[0 = non-prefetchable,
1 = prefetchable].
The value read in this field is determined by the setting of BAR Configuration Registers of
the associated Physical Function
2S0R1hWhen the BAR is used to define a memory address range, this field indicates whether
the address range is
32-bit or
64-bit
[0 =
32-bit,
1 = 64 bit].
For
64-bit address ranges, the
value in BAR 1 is treated as a continuation of the base address in BAR 0.

The value read in
this field is determined by the setting of BAR Configuration Registers of the associated
Physical Function.
1R7R0hThis bit is hardwired to 0 for both memory and I/O BARs.
0MSIR0hSpecifies whether this BAR defines a memory address range or an I/O address range
[0 =
memory,
1 = I/O].
The value read in this field is determined by the setting of BAR
Configuration Registers of the associated Physical Function

3.5.1.102 PCIE_CORE_PFn_I_VF_BAR_1_REG Register (Offset = 228h + formula) [reset = 0h]

PCIE_CORE_PFn_I_VF_BAR_1_REG is shown in Figure 12-1368 and described in Table 12-2674.

Return to the Summary Table.

This is part of the set of six Virtual Function Base Address Registers defined
by the SR-IOV Specifications. These registers are used to define address ranges for memory
accesses to the Endpoint device. This register may be used to define a range of 32-bit addresses.
During the initial configuration of the device, the configuration program determines the size of
the address range defined by the BAR by writing a pattern of all 1's into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned value.
A value of 0 is returned by the Controller if this BAR is not configured. Otherwise, the number of 1's returned
is based on the length of the BAR.

Offset = 228h + (n * 1000h); where n = 0h to 5h

Table 12-2673 PCIE_CORE_PFn_I_VF_BAR_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0228h + formula
Figure 12-1368 PCIE_CORE_PFn_I_VF_BAR_1_REG Register
313029282726252423222120191817161514131211109876543210
BAMRW
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2674 PCIE_CORE_PFn_I_VF_BAR_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0BAMRWR/W0hThis field defines the base address of the memory address range.
The number of implemented
bits in this field determines the BAR aperture setting of BAR Configuration Registers of
the associated Physical Function.
All other bits are not writeable, and are read as 0's.

3.5.1.103 PCIE_CORE_PFn_I_VF_BAR_2_REG Register (Offset = 22Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_VF_BAR_2_REG is shown in Figure 12-1369 and described in Table 12-2676.

Return to the Summary Table.

This is part of the set of six Virtual Function Base Address Registers defined
by the SR-IOV Specifications. These registers are used to define address ranges for memory
accesses to the Endpoint device. This register may be used to define a range of 32-bit addresses,
or paired with the next adjacent register to define a 64-bit address range.
During the initial configuration of the device, the configuration program determines the size of
the address range defined by the BAR by writing a pattern of all 1's into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned value.
A value of 0 is returned by the Controller if this BAR is not configured. Otherwise, the number of 1's returned
is based on the length of the BAR.

Offset = 22Ch + (n * 1000h); where n = 0h to 5h

Table 12-2675 PCIE_CORE_PFn_I_VF_BAR_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 022Ch + formula
Figure 12-1369 PCIE_CORE_PFn_I_VF_BAR_2_REG Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2676 PCIE_CORE_PFn_I_VF_BAR_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.104 PCIE_CORE_PFn_I_VF_BAR_3_REG Register (Offset = 230h + formula) [reset = 0h]

PCIE_CORE_PFn_I_VF_BAR_3_REG is shown in Figure 12-1370 and described in Table 12-2678.

Return to the Summary Table.

This is part of the set of six Virtual Function Base Address Registers defined
by the SR-IOV Specifications. These registers are used to define address ranges for memory
accesses to the Endpoint device. This register may be used to define a range of 32-bit addresses.
During the initial configuration of the device, the configuration program determines the size of
the address range defined by the BAR by writing a pattern of all 1's into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned value.
A value of 0 is returned by the Controller if this BAR is not configured. Otherwise, the number of 1's returned
is based on the length of the BAR.

Offset = 230h + (n * 1000h); where n = 0h to 5h

Table 12-2677 PCIE_CORE_PFn_I_VF_BAR_3_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0230h + formula
Figure 12-1370 PCIE_CORE_PFn_I_VF_BAR_3_REG Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2678 PCIE_CORE_PFn_I_VF_BAR_3_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.105 PCIE_CORE_PFn_I_VF_BAR_4_REG Register (Offset = 234h + formula) [reset = 0h]

PCIE_CORE_PFn_I_VF_BAR_4_REG is shown in Figure 12-1371 and described in Table 12-2680.

Return to the Summary Table.

This is part of the set of six Virtual Function Base Address Registers defined
by the SR-IOV Specifications. These registers are used to define address ranges for memory
accesses to the Endpoint device. This register may be used to define a range of 32-bit addresses,
or paired with the next adjacent register to define a 64-bit address range.
During the initial configuration of the device, the configuration program determines the size of
the address range defined by the BAR by writing a pattern of all 1's into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned value.
A value of 0 is returned by the Controller if this BAR is not configured. Otherwise, the number of 1's returned
is based on the length of the BAR.

Offset = 234h + (n * 1000h); where n = 0h to 5h

Table 12-2679 PCIE_CORE_PFn_I_VF_BAR_4_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0234h + formula
Figure 12-1371 PCIE_CORE_PFn_I_VF_BAR_4_REG Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2680 PCIE_CORE_PFn_I_VF_BAR_4_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.106 PCIE_CORE_PFn_I_VF_BAR_5_REG Register (Offset = 238h + formula) [reset = 0h]

PCIE_CORE_PFn_I_VF_BAR_5_REG is shown in Figure 12-1372 and described in Table 12-2682.

Return to the Summary Table.

This is part of the set of six Virtual Function Base Address Registers defined
by the SR-IOV Specifications. These registers are used to define address ranges for memory
accesses to the Endpoint device. This register may be used to define a range of 32-bit addresses.
During the initial configuration of the device, the configuration program determines the size of
the address range defined by the BAR by writing a pattern of all 1's into the BAR, reading back
from the BAR, and noting the position of the first 1 (the most significant) in the returned value.
A value of 0 is returned by the Controller if this BAR is not configured. Otherwise, the number of 1's returned
is based on the length of the BAR.

Offset = 238h + (n * 1000h); where n = 0h to 5h

Table 12-2681 PCIE_CORE_PFn_I_VF_BAR_5_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0238h + formula
Figure 12-1372 PCIE_CORE_PFn_I_VF_BAR_5_REG Register
313029282726252423222120191817161514131211109876543210
R7
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2682 PCIE_CORE_PFn_I_VF_BAR_5_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R7R0hThis field is reserved at power-on.
This can be changed using BAR configuration regsiter in LM space.

3.5.1.107 PCIE_CORE_PFn_I_VF_MIGRATION_STATE_ARR_OFFSET_REG Register (Offset = 23Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_VF_MIGRATION_STATE_ARR_OFFSET_REG is shown in Figure 12-1373 and described in Table 12-2684.

Return to the Summary Table.

Not implemented

Offset = 23Ch + (n * 1000h); where n = 0h to 5h

Table 12-2683 PCIE_CORE_PFn_I_VF_MIGRATION_STATE_ARR_OFFSET_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 023Ch
Figure 12-1373 PCIE_CORE_PFn_I_VF_MIGRATION_STATE_ARR_OFFSET_REG Register
313029282726252423222120191817161514131211109876543210
MSAOR
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2684 PCIE_CORE_PFn_I_VF_MIGRATION_STATE_ARR_OFFSET_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0MSAORR0hN/A

3.5.1.108 PCIE_CORE_PFn_RSVD_090_09C Register (Offset = 240h + formula) [reset = 0h]

PCIE_CORE_PFn_RSVD_090_09C is shown in Figure 12-1374 and described in Table 12-2686.

Return to the Summary Table.

Reserved

Offset = 240h + (n * 1000h); where n = 0h to 5h

Table 12-2685 PCIE_CORE_PFn_RSVD_090_09C Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0240h + formula
Figure 12-1374 PCIE_CORE_PFn_RSVD_090_09C Register
313029282726252423222120191817161514131211109876543210
RSVD
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2686 PCIE_CORE_PFn_RSVD_090_09C Register Field Descriptions
BitFieldTypeResetDescription
31-0RSVDR0hReserved

3.5.1.109 PCIE_CORE_PF0_I_SEC_PCIE_CAP_HDR_REG Register (Offset = 300h) [reset = 40010019h]

PCIE_CORE_PF0_I_SEC_PCIE_CAP_HDR_REG is shown in Figure 12-1375 and described in Table 12-2688.

Return to the Summary Table.

This register contains the PCI Express Extended Capability ID for the Secondary PCI
Express Extended Capability, its capability version, and the pointer to the next capability
structure. This register is implemented only in the configuration space of PF 0.

Table 12-2687 PCIE_CORE_PF0_I_SEC_PCIE_CAP_HDR_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0300h
Figure 12-1375 PCIE_CORE_PF0_I_SEC_PCIE_CAP_HDR_REG Register
313029282726252423222120191817161514131211109876543210
NCOCVPECI
R/W-400hR/W-1hR-19h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2688 PCIE_CORE_PF0_I_SEC_PCIE_CAP_HDR_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W400hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified independently for each PF from the local
management bus.
15-0PECIR19hThis field is hardwired to the Capability ID assigned by PCI SIG to the Secondary PCI
Express Capability

3.5.1.110 PCIE_CORE_PF0_I_LINK_CONTROL3_REG Register (Offset = 304h) [reset = 0h]

PCIE_CORE_PF0_I_LINK_CONTROL3_REG is shown in Figure 12-1376 and described in Table 12-2690.

Return to the Summary Table.

Link Control3 Register.

Table 12-2689 PCIE_CORE_PF0_I_LINK_CONTROL3_REG Instances
Figure 12-1376 PCIE_CORE_PF0_I_LINK_CONTROL3_REG Register
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2690 PCIE_CORE_PF0_I_LINK_CONTROL3_REG Register Field Descriptions

3.5.1.111 PCIE_CORE_PF0_I_LANE_ERROR_STATUS_REG Register (Offset = 308h) [reset = 0h]

PCIE_CORE_PF0_I_LANE_ERROR_STATUS_REG is shown in Figure 12-1377 and described in Table 12-2692.

Return to the Summary Table.

This register contains one bit per lane indicating the physical-layer error status of
the corresponding lane. A 1 indicates that a physical-layer error was detected by the Controller in
the corresponding lane. The error can be cleared by writing a 1 into the bit position, either
through a Configuration Write transaction from the link or from the local management bus.
The following errors are reported in this status bit:
(i) Parity error detected in Gen3 SKP OS,
(ii)Loss of Block Alignment in the lane.

Table 12-2691 PCIE_CORE_PF0_I_LANE_ERROR_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0308h
Figure 12-1377 PCIE_CORE_PF0_I_LANE_ERROR_STATUS_REG Register
31302928272625242322212019181716
R0
R-0h
1514131211109876543210
R0LES
R-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2692 PCIE_CORE_PF0_I_LANE_ERROR_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4R0R0hN/A
3-0LESR/W1C0hEach of these bits indicates the error status for the corresponding lane.
STICKY.

3.5.1.112 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG0 Register (Offset = 30Ch) [reset = 7F007F00h]

PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG0 is shown in Figure 12-1378 and described in Table 12-2694.

Return to the Summary Table.

This register contains the 8.0GT/s Transmitter Preset and the Receiver Preset Hint values for
lanes 0 and 1, received from the Upstream Device during the Link Equalization procedure.

Table 12-2693 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 030Ch
Figure 12-1378 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG0 Register
3130292827262524
R3UPRPH1UPTP1
R-0hR-7hR-Fh
2322212019181716
R2_1R2
R-0hR-0h
15141312111098
R1UPRPH0UPTP0
R-0hR-7hR-Fh
76543210
R0_1R0
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2694 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31R3R0hReserved
30-28UPRPH1R7h8.0GT/s Lane 1 Receiver Preset Hint value received from the upstream device.
27-24UPTP1RFh8.0GT/s Lane 1 Transmitter Preset value received from the upstream device.
23R2_1R0hReserved
22-16R2R0hReserved
15R1R0hReserved
14-12UPRPH0R7h8.0GT/s Lane 0 Receiver Preset Hint value received from the upstream device.
11-8UPTP0RFh8.0GT/s Lane 0 Transmitter Preset value received from the upstream device.
7R0_1R0hReserved
6-0R0R0hReserved

3.5.1.113 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG1 Register (Offset = 310h) [reset = 7F7F7F7Fh]

PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG1 is shown in Figure 12-1551 and described in Table 12-3044.

Return to the Summary Table.

This register contains the 8.0GT/s Transmitter Preset and the Receiver Preset Hint values for lanes 2 and 3, for use during the Link Equalization procedure.

Table 12-2695 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0310h
Figure 12-1379 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG1 Register
3130292827262524
R3UPRPH1UPTP1
R-0hR-7hR-Fh
2322212019181716
R2_1DNRPH1DNTP1
R-0hR-7hR-Fh
15141312111098
R1UPRPH0UPTP0
R-0hR-7hR-Fh
76543210
R0_1DNRPH0DNTP0
R-0hR-7hR-Fh
Table 12-2696 PCIE_CORE_PF0_I_LANE_EQUALIZATION_CONTROL_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31R3R0hReserved
30-28UPRPH1R7h8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 3.
The remote node may use this value to adapt its receiver at the start of the link equalization procedure.
27-24UPTP1RFh8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 3.
The remote node uses this value to set up its transmitter at the start of the link equalization procedure.
23R2_1R0hReserved
22-20DNRPH1R7h8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 3.
The Controller uses this value to set up the receiver attached to Lane 3
19-16DNTP1RFh8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 3.
The Controller uses this value to set up the Lane 3 transmitter during link equalization.
15R1R0hReserved
14-12UPRPH0R7h8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 2.
The remote node may use this value to adapt its receiver at the start of the link equalization procedure.
11-8UPTP0RFh8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 2.
The remote node uses this value to set up its transmitter at the start of the link equalization procedure.
7R0_1R0hReserved
6-4DNRPH0R7h8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 2.
The Controller uses this value to set up the receiver attached to Lane 2
3-0DNTP0RFh8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 2.
The Controller uses this value to set up the Lane 2 transmitter during link equalization.

3.5.1.114 PCIE_CORE_PFn_I_VSEC_HEADER_REG Register (Offset = 400h + formula) [reset = 4401000Bh]

PCIE_CORE_PFn_I_VSEC_HEADER_REG is shown in Figure 12-1380 and described in Table 12-2698.

Return to the Summary Table.

The Vendor-Specific Capability allows device vendors to use the Capability mechanism for vendor specific information.

Offset = 400h + (n * 1000h); where n = 0h to 5h

Table 12-2697 PCIE_CORE_PFn_I_VSEC_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0400h + formula
Figure 12-1380 PCIE_CORE_PFn_I_VSEC_HEADER_REG Register
313029282726252423222120191817161514131211109876543210
NCOCVPECI
R/W-440hR/W-1hR/W-Bh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2698 PCIE_CORE_PFn_I_VSEC_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W440hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified independently for each PF from the local
management bus.
15-0PECIR/WBhThis field is hardwired to the Capability ID assigned by PCI SIG to the
Vendor-Specific Extended Capability.

3.5.1.115 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_HEADER_REG Register (Offset = 404h + formula) [reset = 01010001h]

PCIE_CORE_PFn_I_VENDOR_SPECIFIC_HEADER_REG is shown in Figure 12-1381 and described in Table 12-2700.

Return to the Summary Table.

Vendor-Specific Header Register.

Offset = 404h + (n * 1000h); where n = 0h to 5h

Table 12-2699 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0404h + formula
Figure 12-1381 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_HEADER_REG Register
313029282726252423222120191817161514131211109876543210
VLVRVI
R/W-10hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2700 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20VLR/W10hTotal byte count [in hex format] of the VSEC structure, including the Vendor-Specific
Capability Header, the Vendor-Specific Header and the Vendor-Specific registers.
This field
can be written from the local management bus independently or each PF.
19-16VRR/W1hVendor-defined version number for the VSEC structure.
This field can be written from
the local management bus independently or each PF.
15-0VIR/W1hThis field contains a vendor defined ID number that indicates the nature and format of
the information in the Vendor-Specific Capability Structure.
This field can be written from
the local management bus independently or each PF.

3.5.1.116 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG Register (Offset = 408h + formula) [reset = 0h]

PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG is shown in Figure 12-1382 and described in Table 12-2702.

Return to the Summary Table.

This contains the first 4 Bytes of Vendor-Specific Register space. In the current
implementation, the first 4 Bytes of Vendor Specific Registers is called as Vendor Specific Control Register and is described in the fields below.

Offset = 408h + (n * 1000h); where n = 0h to 5h

Table 12-2701 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0408h + formula
Figure 12-1382 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG Register
31302928272625242322212019181716
VSEC_COUT
R/W-0h
1514131211109876543210
VSEC_COUTHTIVSEC_CIN
R/W-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2702 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-9VSEC_COUTR/W0hThe state of these bits drive the output pins Fx_VSEC_CONTROL_OUT [ where x is the
function number].
These are implemented as register bits that can be
read and written by the host through a Config transaction, or via the local management
interface.
8HTIR/W0hThe state of this bit drives the output pins Fx_VSEC_INTERRUPT_OUT [ where x is the
function number].
It can be used by the host to signal a
software-driven interrupt to the application logic outside the Controller.
This bit may be read and
written by the host through a Config transaction, or via the local management interface.
7-0VSEC_CINR0hThe
8-bit value read from this field of PFx reflects the setting of
Fx_VSEC_CONTROL_IN
[7:0] input to the Controller.
This field can also be read from the local management bus

3.5.1.117 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_DATA_REG0 Register (Offset = 40Ch + formula) [reset = 0h]

PCIE_CORE_PFn_I_VENDOR_SPECIFIC_DATA_REG0 is shown in Figure 12-1383 and described in Table 12-2704.

Return to the Summary Table.

This contains the Bytes 4, 5, 6, 7 of Vendor-Specific Register space. In the current
implementation, the these 4 Bytes of Vendor Specific Registers are called as Vendor Specific Data Register 0 and is described below.

Offset = 40Ch + (n * 1000h); where n = 0h to 5h

Table 12-2703 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_DATA_REG0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 040Ch + formula
Figure 12-1383 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_DATA_REG0 Register
313029282726252423222120191817161514131211109876543210
GPD
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2704 PCIE_CORE_PFn_I_VENDOR_SPECIFIC_DATA_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-0GPDR/W0hThese bits are implemented as register bits that can be read and written by the host
through a Config transaction, or via the local management interface.
Their use is
application-dependent.

3.5.1.118 PCIE_CORE_PFn_I_PASID_HEADER_REG Register (Offset = 440h + formula) [reset = 4C01001Bh]

PCIE_CORE_PFn_I_PASID_HEADER_REG is shown in Figure 12-1384 and described in Table 12-2706.

Return to the Summary Table.

The presence of a PASID Extended Capability indicates that the Endpoint supports sending and
receiving TLPs containing a PASID TLP Prefix.

Offset = 440h + (n * 1000h); where n = 0h to 5h

Table 12-2705 PCIE_CORE_PFn_I_PASID_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0440h + formula
Figure 12-1384 PCIE_CORE_PFn_I_PASID_HEADER_REG Register
313029282726252423222120191817161514131211109876543210
NCOCVPECI
R/W-4C0hR/W-1hR-1Bh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2706 PCIE_CORE_PFn_I_PASID_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W4C0hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified independently for each PF from the local
management bus.
15-0PECIR1BhThis field is hardwired to the Capability ID assigned by PCI SIG to the
PASID Capability.

3.5.1.119 PCIE_CORE_PFn_I_PASID_CAP_REG Register (Offset = 444h + formula) [reset = 1406h]

PCIE_CORE_PFn_I_PASID_CAP_REG is shown in Figure 12-1385 and described in Table 12-2708.

Return to the Summary Table.

PASID Capability Header fields are described below:

Offset = 444h + (n * 1000h); where n = 0h to 5h

Table 12-2707 PCIE_CORE_PFn_I_PASID_CAP_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0444h + formula
Figure 12-1385 PCIE_CORE_PFn_I_PASID_CAP_REG Register
3130292827262524
R31
R-0h
2322212019181716
R31PRMEEXPEPASE
R-0hR/W-0hR/W-0hR/W-0h
15141312111098
R15MPSW
R-0hR/W-14h
76543210
RSVD2PRMSEXPSRSVD1
R-0hR/W-1hR/W-1hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2708 PCIE_CORE_PFn_I_PASID_CAP_REG Register Field Descriptions
BitFieldTypeResetDescription
31-19R31R0hReserved
18PRMER/W0hIf set, the Endpoint is permitted to send requests that have the Privileged Mode Requested bit set.

If clear, the Endpoint is not permitted to do so.
17EXPER/W0hIf set, the Endpoint is permitted to send requests that have the Execute Requested bit set.

If clear, the Endpoint is not permitted to do so.
16PASER/W0hIf set, the Endpoint is permitted to send and receive TLPs that contain a PASID TLP Prefix.
If clear, the Endpoint is not permitted to do so.
15-13R15R0hReserved
12-8MPSWR/W14hIndicates the width of the PASID field supported by the Endpoint.
The value indicates support
for PASID values 0 through 2n-1 [inclusive].
The value 0 indicates support for a single PASID [0].

The value 20 indicates support for all PASID values [20 bits].
This field must be between 0 and 20
[inclusive].
7-3RSVD2R0hThese bits are currently reserved.
These are implemented as register bits that can be
read and written by the host through a Config transaction, or via the local management
interface.
2PRMSR/W1hIf set, the Endpoint supports operating in Privileged and Non-Privileged modes, and supports
sending requests that have the Privileged Mode Requested bit set.
If clear, the Endpoint should never
set the Privileged Mode Requested bit.
1EXPSR/W1hIf set, the Endpoint supports sending memory requests that have the Execute Requested bit set.
If clear, the Endpoint should never set the Execute Requested bit.
0RSVD1R0hThese bits are currently reserved.
These are implemented as register bits that can be
read and written by the host through a Config transaction, or via the local management
interface.

3.5.1.120 PCIE_CORE_PF0_I_VC_ENH_CAP_HEADER_REG Register (Offset = 4C0h) [reset = 5C010002h]

PCIE_CORE_PF0_I_VC_ENH_CAP_HEADER_REG is shown in Figure 12-1386 and described in Table 12-2710.

Return to the Summary Table.

This is the first register in the Virtual Channel Capability Structure. The VC Capability is present only in
the configuration space of Physical Function 0. This register contains the PCI Express Extended
Capability ID, the capability version, and the pointer to the next capability structure.

Table 12-2709 PCIE_CORE_PF0_I_VC_ENH_CAP_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04C0h
Figure 12-1386 PCIE_CORE_PF0_I_VC_ENH_CAP_HEADER_REG Register
313029282726252423222120191817161514131211109876543210
NCOCVPECID
R/W-5C0hR/W-1hR-2h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2710 PCIE_CORE_PF0_I_VC_ENH_CAP_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W5C0hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified independently for each PF from the local
management bus.
15-0PECIDR2hThis field is hardwired to the Capability ID assigned by PCI SIG to the VC
Capability.

3.5.1.121 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_1 Register (Offset = 4C4h) [reset = 3h]

PCIE_CORE_PF0_I_PORT_VC_CAP_REG_1 is shown in Figure 12-1387 and described in Table 12-2712.

Return to the Summary Table.

This register has fields that describe the capabilities of the device with respect to the virtual channels.

Table 12-2711 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04C4h
Figure 12-1387 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_1 Register
313029282726252423222120191817161514131211109876543210
R0EVC
R-0hR-3h
LEGEND: R = Read Only; -n = value after reset
Table 12-2712 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_1 Register Field Descriptions
BitFieldTypeResetDescription
31-3R0R0hN/A
2-0EVCR3hIndicates the number of Virtual Channels in addition to the default VC supported by
the device.
This field is valid for all functions.

3.5.1.122 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_2 Register (Offset = 4C8h) [reset = 0h]

PCIE_CORE_PF0_I_PORT_VC_CAP_REG_2 is shown in Figure 12-1388 and described in Table 12-2714.

Return to the Summary Table.

This register has fields that describe the capabilities of the device with respect to the virtual channels.
This register is not implemented. A read from this location returns all zeroes.

Table 12-2713 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04C8h
Figure 12-1388 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_2 Register
313029282726252423222120191817161514131211109876543210
R1
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2714 PCIE_CORE_PF0_I_PORT_VC_CAP_REG_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0R1R0hN/A

3.5.1.123 PCIE_CORE_PF0_I_PORT_VC_CTRL_STS_REG Register (Offset = 4CCh) [reset = 0h]

PCIE_CORE_PF0_I_PORT_VC_CTRL_STS_REG is shown in Figure 12-1389 and described in Table 12-2716.

Return to the Summary Table.

This location contains the 16-bit VC Control Register and the 16-bit VC Status Register. These registers
are not implemented. A read from this location returns all zeroes.

Table 12-2715 PCIE_CORE_PF0_I_PORT_VC_CTRL_STS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04CCh
Figure 12-1389 PCIE_CORE_PF0_I_PORT_VC_CTRL_STS_REG Register
313029282726252423222120191817161514131211109876543210
R2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2716 PCIE_CORE_PF0_I_PORT_VC_CTRL_STS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R2R0hN/A

3.5.1.124 PCIE_CORE_PF0_I_VC_RES_CAP_REG_0 Register (Offset = 4D0h) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_CAP_REG_0 is shown in Figure 12-1390 and described in Table 12-2718.

Return to the Summary Table.

This register describes the capabilities associated with VC 0. This register is not implemented. A read
from this location returns all zeroes.

Table 12-2717 PCIE_CORE_PF0_I_VC_RES_CAP_REG_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04D0h
Figure 12-1390 PCIE_CORE_PF0_I_VC_RES_CAP_REG_0 Register
313029282726252423222120191817161514131211109876543210
R3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2718 PCIE_CORE_PF0_I_VC_RES_CAP_REG_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0R3R0hN/A

3.5.1.125 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_0 Register (Offset = 4D4h) [reset = 800000FFh]

PCIE_CORE_PF0_I_VC_RES_CTRL_REG_0 is shown in Figure 12-1391 and described in Table 12-2720.

Return to the Summary Table.

This register contains bits to configure VC 0.

Table 12-2719 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04D4h
Figure 12-1391 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_0 Register
3130292827262524
VCENR6VCI
R-1hR-0hR-0h
2322212019181716
R5PARSLPAT
R-0hR-0hR-0h
15141312111098
R4
R-0h
76543210
TVMTVM0
R/W-7FhR-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2720 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_0 Register Field Descriptions
BitFieldTypeResetDescription
31VCENR1hSoftware uses this bit to enable the VC.
For VC0 this bit is hardwired to 1.
30-27R6R0hN/A
26-24VCIR0hVC ID assigned to VC0.
For the VC0, this field is read-only and it is hardwired to 00b.
For non VC0 case, it is allowed to use any VC-ID.
This VC-ID has to be unique across all VCs.
This must not be same as VC0's ID[VC0 ID=0].
23-20R5R0hN/A
19-17PARSR0hConfigures the VC to use a specific port arbitration scheme.
This field is not implemented, and hardwired
to 0.
16LPATR0hUpdates the port arbitration logic from the Port Arbitration Table for VC 0.
This bit is not implemented,
and hardwired to 0.
15-8R4R0hN/A
7-1TVMR/W7FhIndicates the TCs that are mapped to this VC.
When bit 0 of this field is set, it indicates that TC 0 is
mapped to VC 0.By default, all TCs are mapped to VC 0.
0TVM0R1hIndicates the TC0 always mapped to VC0.

3.5.1.126 PCIE_CORE_PF0_I_VC_RES_STS_REG_0 Register (Offset = 4D8h) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_STS_REG_0 is shown in Figure 12-1392 and described in Table 12-2722.

Return to the Summary Table.

This register contains status bits associated with VC 0.

Table 12-2721 PCIE_CORE_PF0_I_VC_RES_STS_REG_0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04D8h
Figure 12-1392 PCIE_CORE_PF0_I_VC_RES_STS_REG_0 Register
3130292827262524
R7
R-0h
2322212019181716
R7
R-0h
15141312111098
R7
R-0h
76543210
R7VCNPPATS
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2722 PCIE_CORE_PF0_I_VC_RES_STS_REG_0 Register Field Descriptions
BitFieldTypeResetDescription
31-2R7R0hN/A
1VCNPR0hThis indicates whether the Virtual Channel negotiation is in pending state.
The value of this bit is defined
only when the link is in the DL_Active state and Virtual Channel is enabled.

When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation.
This
bit is cleared by hardware after the VC negotiation is complete.
0PATSR0hThis is not implemented and hardwired to 0.

3.5.1.127 PCIE_CORE_PF0_I_VC_RES_CAP_REG_1 Register (Offset = 4DCh) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_CAP_REG_1 is shown in Figure 12-1393 and described in Table 12-2724.

Return to the Summary Table.

This register describes the capabilities associated with VC 1. This register is not implemented. A read
from this location returns all zeroes.

Table 12-2723 PCIE_CORE_PF0_I_VC_RES_CAP_REG_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04DCh
Figure 12-1393 PCIE_CORE_PF0_I_VC_RES_CAP_REG_1 Register
313029282726252423222120191817161514131211109876543210
R3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2724 PCIE_CORE_PF0_I_VC_RES_CAP_REG_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0R3R0hN/A

3.5.1.128 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_1 Register (Offset = 4E0h) [reset = 01000000h]

PCIE_CORE_PF0_I_VC_RES_CTRL_REG_1 is shown in Figure 12-1394 and described in Table 12-2726.

Return to the Summary Table.

This register contains bits to configure VC 1.

Table 12-2725 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04E0h
Figure 12-1394 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_1 Register
3130292827262524
VCENR6VCI
R/W-0hR-0hR/W-1h
2322212019181716
R5PARSLPAT
R-0hR-0hR-0h
15141312111098
R4
R-0h
76543210
TVMTVM0
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2726 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_1 Register Field Descriptions
BitFieldTypeResetDescription
31VCENR/W0hSoftware uses this bit to enable the VC.
For VC0 this bit is hardwired to 1.
30-27R6R0hN/A
26-24VCIR/W1hVC ID assigned to VC1.
For the VC0, this field is read-only and it is hardwired to 00b.
For non VC0 case, it is allowed to use any VC-ID.
This VC-ID has to be unique across all VCs.
This must not be same as VC0's ID[VC0 ID=0].
23-20R5R0hN/A
19-17PARSR0hConfigures the VC to use a specific port arbitration scheme.
This field is not implemented, and hardwired
to 0.
16LPATR0hUpdates the port arbitration logic from the Port Arbitration Table for VC 1.
This bit is not implemented,
and hardwired to 0.
15-8R4R0hN/A
7-1TVMR/W0hIndicates the TCs that are mapped to this VC.
When bit 1 of this field is set, it indicates that TC 1 is
mapped to VC 1.By default, all TCs are mapped to VC 0.
0TVM0R0hIndicates the TC0 always mapped to VC0.

3.5.1.129 PCIE_CORE_PF0_I_VC_RES_STS_REG_1 Register (Offset = 4E4h) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_STS_REG_1 is shown in Figure 12-1395 and described in Table 12-2728.

Return to the Summary Table.

This register contains status bits associated with VC 1.

Table 12-2727 PCIE_CORE_PF0_I_VC_RES_STS_REG_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04E4h
Figure 12-1395 PCIE_CORE_PF0_I_VC_RES_STS_REG_1 Register
3130292827262524
R7
R-0h
2322212019181716
R7
R-0h
15141312111098
R7
R-0h
76543210
R7VCNPPATS
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2728 PCIE_CORE_PF0_I_VC_RES_STS_REG_1 Register Field Descriptions
BitFieldTypeResetDescription
31-2R7R0hN/A
1VCNPR0hThis indicates whether the Virtual Channel negotiation is in pending state.
The value of this bit is defined
only when the link is in the DL_Active state and Virtual Channel is enabled.

When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation.
This
bit is cleared by hardware after the VC negotiation is complete.
0PATSR0hThis is not implemented and hardwired to 0.

3.5.1.130 PCIE_CORE_PF0_I_VC_RES_CAP_REG_2 Register (Offset = 4E8h) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_CAP_REG_2 is shown in Figure 12-1396 and described in Table 12-2730.

Return to the Summary Table.

This register describes the capabilities associated with VC 2. This register is not implemented. A read
from this location returns all zeroes.

Table 12-2729 PCIE_CORE_PF0_I_VC_RES_CAP_REG_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04E8h
Figure 12-1396 PCIE_CORE_PF0_I_VC_RES_CAP_REG_2 Register
313029282726252423222120191817161514131211109876543210
R3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2730 PCIE_CORE_PF0_I_VC_RES_CAP_REG_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0R3R0hN/A

3.5.1.131 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_2 Register (Offset = 4ECh) [reset = 02000000h]

PCIE_CORE_PF0_I_VC_RES_CTRL_REG_2 is shown in Figure 12-1397 and described in Table 12-2732.

Return to the Summary Table.

This register contains bits to configure VC 2.

Table 12-2731 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04ECh
Figure 12-1397 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_2 Register
3130292827262524
VCENR6VCI
R/W-0hR-0hR/W-2h
2322212019181716
R5PARSLPAT
R-0hR-0hR-0h
15141312111098
R4
R-0h
76543210
TVMTVM0
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2732 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_2 Register Field Descriptions
BitFieldTypeResetDescription
31VCENR/W0hSoftware uses this bit to enable the VC.
For VC0 this bit is hardwired to 1.
30-27R6R0hN/A
26-24VCIR/W2hVC ID assigned to VC2.
For the VC0, this field is read-only and it is hardwired to 00b.
For non VC0 case, it is allowed to use any VC-ID.
This VC-ID has to be unique across all VCs.
This must not be same as VC0's ID[VC0 ID=0].
23-20R5R0hN/A
19-17PARSR0hConfigures the VC to use a specific port arbitration scheme.
This field is not implemented, and hardwired
to 0.
16LPATR0hUpdates the port arbitration logic from the Port Arbitration Table for VC 2.
This bit is not implemented,
and hardwired to 0.
15-8R4R0hN/A
7-1TVMR/W0hIndicates the TCs that are mapped to this VC.
When bit 2 of this field is set, it indicates that TC 2 is
mapped to VC 2.By default, all TCs are mapped to VC 0.
0TVM0R0hIndicates the TC0 always mapped to VC0.

3.5.1.132 PCIE_CORE_PF0_I_VC_RES_STS_REG_2 Register (Offset = 4F0h) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_STS_REG_2 is shown in Figure 12-1398 and described in Table 12-2734.

Return to the Summary Table.

This register contains status bits associated with VC 2.

Table 12-2733 PCIE_CORE_PF0_I_VC_RES_STS_REG_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04F0h
Figure 12-1398 PCIE_CORE_PF0_I_VC_RES_STS_REG_2 Register
3130292827262524
R7
R-0h
2322212019181716
R7
R-0h
15141312111098
R7
R-0h
76543210
R7VCNPPATS
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2734 PCIE_CORE_PF0_I_VC_RES_STS_REG_2 Register Field Descriptions
BitFieldTypeResetDescription
31-2R7R0hN/A
1VCNPR0hThis indicates whether the Virtual Channel negotiation is in pending state.
The value of this bit is defined
only when the link is in the DL_Active state and Virtual Channel is enabled.

When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation.
This
bit is cleared by hardware after the VC negotiation is complete.
0PATSR0hThis is not implemented and hardwired to 0.

3.5.1.133 PCIE_CORE_PF0_I_VC_RES_CAP_REG_3 Register (Offset = 4F4h) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_CAP_REG_3 is shown in Figure 12-1399 and described in Table 12-2736.

Return to the Summary Table.

This register describes the capabilities associated with VC 3. This register is not implemented. A read
from this location returns all zeroes.

Table 12-2735 PCIE_CORE_PF0_I_VC_RES_CAP_REG_3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04F4h
Figure 12-1399 PCIE_CORE_PF0_I_VC_RES_CAP_REG_3 Register
313029282726252423222120191817161514131211109876543210
R3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2736 PCIE_CORE_PF0_I_VC_RES_CAP_REG_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0R3R0hN/A

3.5.1.134 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_3 Register (Offset = 4F8h) [reset = 03000000h]

PCIE_CORE_PF0_I_VC_RES_CTRL_REG_3 is shown in Figure 12-1400 and described in Table 12-2738.

Return to the Summary Table.

This register contains bits to configure VC 3.

Table 12-2737 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04F8h
Figure 12-1400 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_3 Register
3130292827262524
VCENR6VCI
R/W-0hR-0hR/W-3h
2322212019181716
R5PARSLPAT
R-0hR-0hR-0h
15141312111098
R4
R-0h
76543210
TVMTVM0
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2738 PCIE_CORE_PF0_I_VC_RES_CTRL_REG_3 Register Field Descriptions
BitFieldTypeResetDescription
31VCENR/W0hSoftware uses this bit to enable the VC.
For VC0 this bit is hardwired to 1.
30-27R6R0hN/A
26-24VCIR/W3hVC ID assigned to VC3.
For the VC0, this field is read-only and it is hardwired to 00b.
For non VC0 case, it is allowed to use any VC-ID.
This VC-ID has to be unique across all VCs.
This must not be same as VC0's ID[VC0 ID=0].
23-20R5R0hN/A
19-17PARSR0hConfigures the VC to use a specific port arbitration scheme.
This field is not implemented, and hardwired
to 0.
16LPATR0hUpdates the port arbitration logic from the Port Arbitration Table for VC 3.
This bit is not implemented,
and hardwired to 0.
15-8R4R0hN/A
7-1TVMR/W0hIndicates the TCs that are mapped to this VC.
When bit 3 of this field is set, it indicates that TC 3 is
mapped to VC 3.By default, all TCs are mapped to VC 0.
0TVM0R0hIndicates the TC0 always mapped to VC0.

3.5.1.135 PCIE_CORE_PF0_I_VC_RES_STS_REG_3 Register (Offset = 4FCh) [reset = 0h]

PCIE_CORE_PF0_I_VC_RES_STS_REG_3 is shown in Figure 12-1401 and described in Table 12-2740.

Return to the Summary Table.

This register contains status bits associated with VC 3.

Table 12-2739 PCIE_CORE_PF0_I_VC_RES_STS_REG_3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 04FCh
Figure 12-1401 PCIE_CORE_PF0_I_VC_RES_STS_REG_3 Register
3130292827262524
R7
R-0h
2322212019181716
R7
R-0h
15141312111098
R7
R-0h
76543210
R7VCNPPATS
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2740 PCIE_CORE_PF0_I_VC_RES_STS_REG_3 Register Field Descriptions
BitFieldTypeResetDescription
31-2R7R0hN/A
1VCNPR0hThis indicates whether the Virtual Channel negotiation is in pending state.
The value of this bit is defined
only when the link is in the DL_Active state and Virtual Channel is enabled.

When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation.
This
bit is cleared by hardware after the VC negotiation is complete.
0PATSR0hThis is not implemented and hardwired to 0.

3.5.1.136 PCIE_CORE_PFn_ATS_CAP_HEADER Register (Offset = 5C0h + formula) [reset = 6401000Fh]

PCIE_CORE_PFn_ATS_CAP_HEADER is shown in Figure 12-1402 and described in Table 12-2742.

Return to the Summary Table.

This location contains the ATS Extended Capabilities Register, its Capability ID, Version,
and a pointer to the next capability.

Offset = 5C0h + (n * 1000h); where n = 0h to 5h

Table 12-2741 PCIE_CORE_PFn_ATS_CAP_HEADER Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 05C0h + formula
Figure 12-1402 PCIE_CORE_PFn_ATS_CAP_HEADER Register
31302928272625242322212019181716
ATSNXTCAPATSCAPVER
R/W-640hR/W-1h
1514131211109876543210
ATSCAPID
R-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2742 PCIE_CORE_PFn_ATS_CAP_HEADER Register Field Descriptions
BitFieldTypeResetDescription
31-20ATSNXTCAPR/W640hIndicates offset to the next PCI Express capability structure.
19-16ATSCAPVERR/W1hSpecifies the SIG assigned value for the version of the capability structure.
15-0ATSCAPIDRFhIndicates the ATS Extended Capability structure.

This field must return a Capability ID of 000Fh indicating that this is an ATS Extended Capability structure.

3.5.1.137 PCIE_CORE_PFn_ATS_CAP_CONTROL Register (Offset = 5C4h + formula) [reset = 61h]

PCIE_CORE_PFn_ATS_CAP_CONTROL is shown in Figure 12-1403 and described in Table 12-2744.

Return to the Summary Table.

ATS Capability and Control Register

Offset = 5C4h + (n * 1000h); where n = 0h to 5h

Table 12-2743 PCIE_CORE_PFn_ATS_CAP_CONTROL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 05C4h + formula
Figure 12-1403 PCIE_CORE_PFn_ATS_CAP_CONTROL Register
3130292827262524
ATSENR30
R/W-0hR-0h
2322212019181716
R30ATSSTU
R-0hR/W-0h
15141312111098
R15
R-0h
76543210
R15ATSGISATSPGALNREQATSINVQD
R-0hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2744 PCIE_CORE_PFn_ATS_CAP_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
31ATSENR/W0hWhen Set, the Function is enabled to cache translations.
Default value is 0b.
30-21R30R0hReserved
20-16ATSSTUR/W0hThis value indicates to the Function the minimum number of

4096-byte blocks that is indicated in a Translation Completions or
Invalidate Requests.
This is a power of 2 multiplier and the number
of blocks is 2STU.

A value of 0 0000b indicates one block and
a value of 1 1111b indicates 231 blocks.
15-7R15R0hReserved
6ATSGISR/W1hIf Set, the Function supports InvalidationRequests that have the Global Invalidate bit Set.

If Clear, the Function ignores the Global Invalidate bit in all Invalidate Requests.
5ATSPGALNREQR/W1hIf Set, indicates the Untranslated Address is always aligned to a 4096 byte boundary.
Controller supports only page aligned request. It always masks the bits and makes it aligned to 4096 for ATS requests.
4-0ATSINVQDR/W1hThe number of Invalidate Requests that the Function
can accept before putting backpressure on the upstream
connection.
If 0 0000b, the Function can accept 32 Invalidate Requests.

3.5.1.138 PCIE_CORE_PFn_ATS_PR_CAP_HEADER Register (Offset = 640h + formula) [reset = 90010013h]

PCIE_CORE_PFn_ATS_PR_CAP_HEADER is shown in Figure 12-1404 and described in Table 12-2746.

Return to the Summary Table.

Page Request Extended Capability Structure is used to configure the Page Request Interface mechanism.

Offset = 640h + (n * 1000h); where n = 0h to 5h

Table 12-2745 PCIE_CORE_PFn_ATS_PR_CAP_HEADER Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0640h + formula
Figure 12-1404 PCIE_CORE_PFn_ATS_PR_CAP_HEADER Register
31302928272625242322212019181716
ATSPRNXCAPATSPRCAPVER
R/W-900hR/W-1h
1514131211109876543210
ATSPRCAPID
R-13h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2746 PCIE_CORE_PFn_ATS_PR_CAP_HEADER Register Field Descriptions
BitFieldTypeResetDescription
31-20ATSPRNXCAPR/W900hThe offset to the next PCI Extended Capability structure.
19-16ATSPRCAPVERR/W1hThis field is a PCI-SIG defined version number that indicates
the version of the Capability structure present.
15-0ATSPRCAPIDR13hIndicates that the associated extended capability structure is a Page
Request Extended Capability.
This field must return a Capability ID of 0013h.

3.5.1.139 PCIE_CORE_PFn_ATS_PR_CONTROL_STATUS Register (Offset = 644h + formula) [reset = X]

PCIE_CORE_PFn_ATS_PR_CONTROL_STATUS is shown in Figure 12-1405 and described in Table 12-2748.

Return to the Summary Table.

ATS Page Request Control Status Register.

Offset = 644h + (n * 1000h); where n = 0h to 5h

Table 12-2747 PCIE_CORE_PFn_ATS_PR_CONTROL_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0644h + formula
Figure 12-1405 PCIE_CORE_PFn_ATS_PR_CONTROL_STATUS Register
3130292827262524
ATSPRGRPRRESERVEDATSPRSTOP
R/W-1hR/W-XR/W-1h
2322212019181716
RESERVEDATSPPRUPRGIATS_PR_RF
R/W-XR/W-0hR/W-0h
15141312111098
RESERVED
R/W-X
76543210
RESERVEDATSPRRSTATSPREN
R/W-XR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2748 PCIE_CORE_PFn_ATS_PR_CONTROL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31ATSPRGRPRR/W1hIf Set, the Function expects a
PASID TLP Prefix on PRG Response Messages when the corresponding
Page Requests had a PASID TLP Prefix.
If Clear, the Function does not
expect PASID TLP Prefixes on any PRG Response Message.
Function behavior is undefined if this bit is Clear and the Function
receives a PRG Response Message with a PASID TLP Prefix.
Function behavior is undefined if this bit is Set and the Function receives
a PRG Response Message with no PASID TLP Prefix when the
corresponding Page Requests had a PASID TLP Prefix
30-25RESERVEDR/WX
24ATSPRSTOPR/W1hWhen this field is Set, the associated page
request interface has stopped issuing additional page
requests and that all previously issued Page Requests
have completed.
When this field is Clear the associated
page request interface either has not stopped or has
stopped issuing new Page Requests but has outstanding
Page Requests.
This field is only meaningful if Enable is
Clear.
If Enable is Set, this field is undefined.
When the Enable field is Cleared, after having been
previously Set, the interface transitions to the stopping
state and Clears this field.
After all page requests currently
outstanding at the Function[s] have completed, this field is
Set and the interface enters the disabled state.
If there
were no outstanding page requests, this field may be Set
immediately when Enable is Cleared.
Resetting the
interface will cause an immediate transition to the disabled
state.
While in the stopping state, receipt of a Response
Failure message will result in the immediate transition to
the disabled state [Setting this field].
For SR-IOV, this field is Set only when all associated
Functions [PF and VFs] have stopped issuing page
requests.
Default value is 1b.
23-18RESERVEDR/WX
17ATSPPRUPRGIR/W0hThis field, when Set, indicates that the Function has received a
PRG Response Message containing a PRG index that has
no matching request.
This field is Set by the Function and
cleared when a one is written to the field.
For SR-IOV, this field is Set in the PF if any associated
Function [PF or VF] receives a PRG Response Message
that does has no matching request.
Default value is 0b.
16ATS_PR_RFR/W0hThis field, when Set, indicates
that the Function has received a PRG Response Message
indicating a Response Failure.
The Function expects no
further responses from the host [any received are ignored].
This field is Set by the Function and Cleared when a one is
written to the field.
For SR-IOV, this field is Set in the PF if any associated
Function [PF or VF] receives a PRG Response Message
indicating Response Failure.
Default value is 0b.
15-2RESERVEDR/WX
1ATSPRRSTR/W0hWhen the Enable field is clear, or is being
cleared in the same register update that sets this field,
writing a 1b to this field, clears the associated
implementation dependent page request credit counter and
pending request state for the associated Page Request
Interface.
No action is initiated if this field is written to 0b or
if this field is written with any value while the Enable field is
Set.
Reads of this field through PCIe link return 0b.
Once this field is written by '1' through pcie link, a vector output[ATS_PR_CONTROL_REG_RESET] of controller gets set.

client logic after clearing the credit counter and pending request state, has to clear this register through local management interface.
0ATSPRENR/W0hThis field, when set, indicates that the Page
Request Interface is allowed to make page requests.

If this field is Clear, the Page Request Interface is not allowed to
issue page requests.

If both this field and the Stopped field are Clear,
then the Page Request Interface will not issue new page requests,
but has outstanding page requests that have been transmitted or
are queued for transmission.
When the Page Request Interface is transitioned from not-Enabled to Enabled,
its status flags [Stopped, Response Failure, and Unexpected Response flags] are cleared.
Enabling a Page Request Interface that has not successfully Stopped has indeterminate results.
Default value is 0b.

3.5.1.140 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_CAPACITY Register (Offset = 648h + formula) [reset = 1h]

PCIE_CORE_PFn_ATS_OUTSTANDING_PR_CAPACITY is shown in Figure 12-1406 and described in Table 12-2750.

Return to the Summary Table.

This register contains the number of outstanding page request messages the associated Page Request
Interface physically supports. This is the upper limit on the number of pages that can be usefully
allocated to the Page Request Interface.

Offset = 648h + (n * 1000h); where n = 0h to 5h

Table 12-2749 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_CAPACITY Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0648h + formula
Figure 12-1406 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_CAPACITY Register
313029282726252423222120191817161514131211109876543210
ATSOUTPRCAP
R/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2750 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_CAPACITY Register Field Descriptions
BitFieldTypeResetDescription
31-0ATSOUTPRCAPR/W1hThis register contains the number of outstanding page request messages the associated Page Request
Interface physically supports.
This is the upper limit on the number of pages that can be usefully
allocated to the Page Request Interface.

3.5.1.141 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_ALLOC Register (Offset = 64Ch + formula) [reset = 0h]

PCIE_CORE_PFn_ATS_OUTSTANDING_PR_ALLOC is shown in Figure 12-1407 and described in Table 12-2752.

Return to the Summary Table.

This register contains the number of outstanding page request messages the associated Page Request
Interface is allowed to issue.

Offset = 64Ch + (n * 1000h); where n = 0h to 5h

Table 12-2751 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_ALLOC Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 064Ch + formula
Figure 12-1407 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_ALLOC Register
313029282726252423222120191817161514131211109876543210
ATSOUTPRALLOC
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2752 PCIE_CORE_PFn_ATS_OUTSTANDING_PR_ALLOC Register Field Descriptions
BitFieldTypeResetDescription
31-0ATSOUTPRALLOCR/W0hThis register contains the number of outstanding page request messages the associated Page Request
Interface is allowed to issue

3.5.1.142 PCIE_CORE_PF0_I_L1_PM_EXT_CAP_HDR Register (Offset = 900h) [reset = 9101001Eh]

PCIE_CORE_PF0_I_L1_PM_EXT_CAP_HDR is shown in Figure 12-1408 and described in Table 12-2754.

Return to the Summary Table.

L1 PM Substates Extended Capability Header Register.
For a multi-Function device associated with an Endpoint implementing L1 PM Substates, this Extended Capability Structure is implemented only in Function 0, and controls the Endpoint's Link behavior on behalf of all the Functions of the device.

Table 12-2753 PCIE_CORE_PF0_I_L1_PM_EXT_CAP_HDR Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0900h
Figure 12-1408 PCIE_CORE_PF0_I_L1_PM_EXT_CAP_HDR Register
313029282726252423222120191817161514131211109876543210
NCOCVPECID
R/W-910hR/W-1hR-1Eh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2754 PCIE_CORE_PF0_I_L1_PM_EXT_CAP_HDR Register Field Descriptions
BitFieldTypeResetDescription
31-20NCOR/W910hIndicates offset to the next PCI Express capability structure.
The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16CVR/W1hSpecifies the SIG assigned value for the version of the capability structure.
This
field is set by default to 1, but can be modified from the local management bus.
15-0PECIDR1EhThis field is hardwired to the Capability ID assigned by PCI SIG
to the L1 PM Substates Extended Capability Structure [001E hex].

3.5.1.143 PCIE_CORE_PF0_I_L1_PM_CAP Register (Offset = 904h) [reset = X]

PCIE_CORE_PF0_I_L1_PM_CAP is shown in Figure 12-1409 and described in Table 12-2756.

Return to the Summary Table.

This register advertises the L1 PM Substates Capabilities.

Table 12-2755 PCIE_CORE_PF0_I_L1_PM_CAP Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0904h
Figure 12-1409 PCIE_CORE_PF0_I_L1_PM_CAP Register
3130292827262524
RESERVED
R/W-X
2322212019181716
R0RESERVEDL1PRTPVRONSCALE
R/W-DhR/W-XR/W-0h
15141312111098
L1PRTCMMDRESTRTIME
R/W-FFh
76543210
RESERVEDL1PMSUPPL1ASPML11SUPPL1ASPML12SUPPL1PML11SUPPL1PML12SUPP
R/W-XR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2756 PCIE_CORE_PF0_I_L1_PM_CAP Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-19R0R/WDhAlong with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time [in us] that this Port requires the port
on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.
The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register.
T Power On is the minimum amount of time that each component must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.
This is to ensure no device is ever actively driving into an unpowered component.This bit can be modified using local management interface.
18RESERVEDR/WX
17-16L1PRTPVRONSCALER/W0hSpecifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register.
Range of Values
00b = 2us
01b = 10us
10b = 100us
11b = Reserved
Default value is 00.This bit can be modified using local management interface.
15-8L1PRTCMMDRESTRTIMER/WFFhTime [in us] required for this Port to re-establish common mode during exit from PM or ASPM L1.2 substate.

This bit can be modified using local management interface.
7-5RESERVEDR/WX
4L1PMSUPPR/W1hWhen Set this bit indicates that this Port supports L1 PM Substates.This bit can be modified using local management interface.
3L1ASPML11SUPPR/W1hWhen Set this bit indicates that ASPM L1.1 is supported.This bit can be modified using local management interface.
2L1ASPML12SUPPR/W1hWhen Set this bit indicates that ASPM L1.2 is supported.This bit can be modified using local management interface.
1L1PML11SUPPR/W1hWhen Set this bit indicates that PCI-PM L1.1 is supported.This bit can be modified using local management interface.
0L1PML12SUPPR/W1hWhen Set this bit indicates that PCI-PM L1.2 is supported.
This bit can be modified using local management interface.

3.5.1.144 PCIE_CORE_PF0_I_L1_PM_CTRL_1 Register (Offset = 908h) [reset = X]

PCIE_CORE_PF0_I_L1_PM_CTRL_1 is shown in Figure 12-1410 and described in Table 12-2758.

Return to the Summary Table.

This register is used to Control ASPM, PCI PM L1 substates.

Table 12-2757 PCIE_CORE_PF0_I_L1_PM_CTRL_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0908h
Figure 12-1410 PCIE_CORE_PF0_I_L1_PM_CTRL_1 Register
3130292827262524
L1THRSHLDSCRESERVEDL1THRSHLDVAL
R/W-0hR/W-XR/W-0h
2322212019181716
L1THRSHLDVAL
R/W-0h
15141312111098
L1CMMDRESTRTIME
R-0h
76543210
RESERVEDL1ASPML11ENL1ASPML12ENL1PML11ENL1PML12EN
R/W-XR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2758 PCIE_CORE_PF0_I_L1_PM_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
31-29L1THRSHLDSCR/W0hThis field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.

000 - Value times 1 ns

001 - Value times 32 ns

010 - Value times 1024 ns

011 - Value times 32,768 ns

100 - Value times 1,048,576 ns

101 - Value times 33,554,422ns

110-
111 - Not permitted
28-26RESERVEDR/WX
25-16L1THRSHLDVALR/W0hAlong with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 [if enabled] or L1.2 [if enabled].
15-8L1CMMDRESTRTIMER0hThis field is reserved for EP.
7-4RESERVEDR/WX
3L1ASPML11ENR/W0hWhen Set this bit enables ASPM L1.1.
2L1ASPML12ENR/W0hWhen Set this bit enables ASPM L1.2.
1L1PML11ENR/W0hWhen Set this bit enables PCI-PM L1.1.
0L1PML12ENR/W0hWhen Set this bit enables PCI-PM L1.2.

3.5.1.145 PCIE_CORE_PF0_I_L1_PM_CTRL_2 Register (Offset = 90Ch) [reset = X]

PCIE_CORE_PF0_I_L1_PM_CTRL_2 is shown in Figure 12-1411 and described in Table 12-2760.

Return to the Summary Table.

L1 PM Substates Control 2 Register

Table 12-2759 PCIE_CORE_PF0_I_L1_PM_CTRL_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 090Ch
Figure 12-1411 PCIE_CORE_PF0_I_L1_PM_CTRL_2 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
L1PWRONVALRESERVEDL1PWRONSC
R/W-5hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-2760 PCIE_CORE_PF0_I_L1_PM_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/WX
7-3L1PWRONVALR/W5hAlong with the T_POWER_ON Scale sets the minimum amount of time [in us] that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.
T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.
2RESERVEDR/WX
1-0L1PWRONSCR/W0hSpecifies the scale used for T_POWER_ON Value.
Range of Values
00b = 2us
01b = 10us
10b = 100us
11b = Reserved

3.5.1.146 PCIE_CORE_PFn_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = 910h + formula) [reset = 92010025h]

PCIE_CORE_PFn_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1412 and described in Table 12-2762.

Return to the Summary Table.

Data Link Feature Extended Capability Structure is used to configure the DL Feature mechanism.

Offset = 910h + (n * 1000h); where n = 0h to 5h

Table 12-2761 PCIE_CORE_PFn_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0910h + formula
Figure 12-1412 PCIE_CORE_PFn_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Register
31302928272625242322212019181716
DLFNXCAPDLFCAPVER
R/W-920hR/W-1h
1514131211109876543210
DLFCAPID
R-25h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2762 PCIE_CORE_PFn_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20DLFNXCAPR/W920hThe offset to the next PCI Extended Capability structure.
19-16DLFCAPVERR/W1hThis field is a PCI-SIG defined version number that indicates
the version of the Capability structure present.
15-0DLFCAPIDR25hIndicates that the associated extended capability structure is the DL Feature
Extended Capability.
This field returns a Capability ID of 0025h.

3.5.1.147 PCIE_CORE_PFn_I_DL_FEATURE_CAPABILITIES_REG Register (Offset = 914h + formula) [reset = 80000001h]

PCIE_CORE_PFn_I_DL_FEATURE_CAPABILITIES_REG is shown in Figure 12-1413 and described in Table 12-2764.

Return to the Summary Table.

Data Link Feature Capabilities Register..

Offset = 914h + (n * 1000h); where n = 0h to 5h

Table 12-2763 PCIE_CORE_PFn_I_DL_FEATURE_CAPABILITIES_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0914h + formula
Figure 12-1413 PCIE_CORE_PFn_I_DL_FEATURE_CAPABILITIES_REG Register
3130292827262524
DLFEXENR0
R/W-1hR-0h
2322212019181716
R0
R-0h
15141312111098
R0
R-0h
76543210
R0DLFCAPVER
R-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2764 PCIE_CORE_PFn_I_DL_FEATURE_CAPABILITIES_REG Register Field Descriptions
BitFieldTypeResetDescription
31DLFEXENR/W1hIf Set, this bit indicates that this Port will enter the DL_Feature
negotiation state prior to Link Initialization.
30-1R0R0hReserved
0DLFCAPVERR/W1hThis bit indicates that this Port supports the Scaled Flow
Control Feature.

3.5.1.148 PCIE_CORE_PFn_I_DL_FEATURE_STATUS_REG Register (Offset = 918h + formula) [reset = 0h]

PCIE_CORE_PFn_I_DL_FEATURE_STATUS_REG is shown in Figure 12-1414 and described in Table 12-2766.

Return to the Summary Table.

Data Link Feature Status Register..

Offset = 918h + (n * 1000h); where n = 0h to 5h

Table 12-2765 PCIE_CORE_PFn_I_DL_FEATURE_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0918h + formula
Figure 12-1414 PCIE_CORE_PFn_I_DL_FEATURE_STATUS_REG Register
3130292827262524
RDLFSVALR1
R-0hR-0h
2322212019181716
R23R0
R-0hR-0h
15141312111098
R0
R-0h
76543210
R0RSFSUP
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2766 PCIE_CORE_PFn_I_DL_FEATURE_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31RDLFSVALR0hThis bit indicates that the Port has received a Data Link Feature
DLLP in state DL_Feature [see Section 3.2.1] and that the
Remote Data Link Feature Supported and Remote Data Link Feature Ack fields are meaningful.
This bit is Cleared on entry to state DL_Inactive.
Default is 0b.
30-24R1R0hReserved
23R23R0hReserved
22-1R0R0hReserved
0RSFSUPR0hThis bit indicates that the Remote end Device supports the Scaled Flow
Control Feature.

3.5.1.149 PCIE_CORE_PF0_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = 920h) [reset = 9C010027h]

PCIE_CORE_PF0_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1415 and described in Table 12-2768.

Return to the Summary Table.

Margining Extended Capability Structure is used to configure the device for Receiver Margining.

Table 12-2767 PCIE_CORE_PF0_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0920h
Figure 12-1415 PCIE_CORE_PF0_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Register
31302928272625242322212019181716
MARNXCAPMARCAPVER
R/W-9C0hR/W-1h
1514131211109876543210
MARCAPID
R-27h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2768 PCIE_CORE_PF0_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20MARNXCAPR/W9C0hThe offset to the next PCI Extended Capability structure.
19-16MARCAPVERR/W1hThis field is a PCI-SIG defined version number that indicates
the version of the Capability structure present.
15-0MARCAPIDR27hIndicates that the associated extended capability structure is the Margining
Extended Capability.
This field returns a Capability ID of 0027h.

3.5.1.150 PCIE_CORE_PF0_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Register (Offset = 924h) [reset = 1h]

PCIE_CORE_PF0_I_MARGINING_PORT_CAPABILITIES_STATUS_REG is shown in Figure 12-1416 and described in Table 12-2770.

Return to the Summary Table.

Margining Port Capabilities and Status Register.

Table 12-2769 PCIE_CORE_PF0_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0924h
Figure 12-1416 PCIE_CORE_PF0_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Register
3130292827262524
R1
R-0h
2322212019181716
R1MSRDYMRDY
R-0hR/W-0hR-0h
15141312111098
R0
R-0h
76543210
R0MARUDS
R-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2770 PCIE_CORE_PF0_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-18R1R0hReserved
17MSRDYR/W0hWhen Margining uses Driver Software is Set, then this bit, when Set, indicates that the required software has performed the required initialization.
The value of this bit is Undefined if Margining users Driver Software is Clear.
The Controller implementation sets the default value of this bit to 0.
The
driver software must initialize the Rx Margining parameters in the Local Management Lane Margining
Registers and then program this bit to 1.
16MRDYR0hIndicates when the Margining feature is ready to accept margining commands.
If the Margining uses Driver Software bit is 1, then the Controller sets this status bit when the Margining Software Ready bit is set and the Link is in Gen4 L0 state.
If the Margining uses Driver Software bit is 0, then the Controller sets this status bit when the Link is in Gen4 L0 state.
15-1R0R0hReserved
0MARUDSR/W1hIf Set, indicates that Margining is partially implemented using Device Driver software.
Margining Software Ready indicates when this software is initialized.
If Clear, Margining does not require device driver software.
The Controller implementation requires driver software to initialize the Rx Margining
parameter values in Local Management Registers for Lane Margining.
Hence, the default value of this bit is set to 1.

3.5.1.151 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG0 Register (Offset = 928h) [reset = 9C38h]

PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG0 is shown in Figure 12-1417 and described in Table 12-2772.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 0.

Table 12-2771 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0928h
Figure 12-1417 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG0 Register
3130292827262524
MPSTS
R/W-0h
2322212019181716
R1UMSTSMTSTSRNSTS
R-0hR/W-0hR/W-0hR/W-0h
15141312111098
MRGPAY
R/W-9Ch
76543210
R0USGMODMRGTYPRCVNUM
R-0hR/W-0hR/W-7hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2772 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-24MPSTSR/W0hMargin Payload Status for Margining Commands.
This field is reset upon DL Down.
23R1R0hReserved
22UMSTSR/W0hUsage Model Status for Margining Commands.
This field is reset upon DL Down.
21-19MTSTSR/W0hMargin Type Status for Margining Commands.
This field is reset upon DL Down.
18-16RNSTSR/W0hReceiver Number Status for Margining Commands.
This field is reset upon DL Down.
15-8MRGPAYR/W9ChMargin Payload for Margining Commands.
This field is reset upon DL Down.
7R0R0hReserved
6USGMODR/W0hUsage Model for Margining Commands.
This field is reset upon DL Down.
5-3MRGTYPR/W7hMargin Type for Margining Commands.
This field is reset upon DL Down.
2-0RCVNUMR/W0hReceiver Number for Margining Commands.
This field is reset upon DL Down.

3.5.1.152 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG1 Register (Offset = 92Ch) [reset = 9C38h]

PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG1 is shown in Figure 12-1418 and described in Table 12-2774.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 1.

Table 12-2773 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 092Ch
Figure 12-1418 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG1 Register
3130292827262524
MPSTS
R/W-0h
2322212019181716
R1UMSTSMTSTSRNSTS
R-0hR/W-0hR/W-0hR/W-0h
15141312111098
MRGPAY
R/W-9Ch
76543210
R0USGMODMRGTYPRCVNUM
R-0hR/W-0hR/W-7hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2774 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-24MPSTSR/W0hMargin Payload Status for Margining Commands.
This field is reset upon DL Down.
23R1R0hReserved
22UMSTSR/W0hUsage Model Status for Margining Commands.
This field is reset upon DL Down.
21-19MTSTSR/W0hMargin Type Status for Margining Commands.
This field is reset upon DL Down.
18-16RNSTSR/W0hReceiver Number Status for Margining Commands.
This field is reset upon DL Down.
15-8MRGPAYR/W9ChMargin Payload for Margining Commands.
This field is reset upon DL Down.
7R0R0hReserved
6USGMODR/W0hUsage Model for Margining Commands.
This field is reset upon DL Down.
5-3MRGTYPR/W7hMargin Type for Margining Commands.
This field is reset upon DL Down.
2-0RCVNUMR/W0hReceiver Number for Margining Commands.
This field is reset upon DL Down.

3.5.1.153 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG2 Register (Offset = 930h) [reset = 9C38h]

PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG2 is shown in Figure 12-1419 and described in Table 12-2776.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 2.

Table 12-2775 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0930h
Figure 12-1419 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG2 Register
3130292827262524
MPSTS
R/W-0h
2322212019181716
R1UMSTSMTSTSRNSTS
R-0hR/W-0hR/W-0hR/W-0h
15141312111098
MRGPAY
R/W-9Ch
76543210
R0USGMODMRGTYPRCVNUM
R-0hR/W-0hR/W-7hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2776 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31-24MPSTSR/W0hMargin Payload Status for Margining Commands.
This field is reset upon DL Down.
23R1R0hReserved
22UMSTSR/W0hUsage Model Status for Margining Commands.
This field is reset upon DL Down.
21-19MTSTSR/W0hMargin Type Status for Margining Commands.
This field is reset upon DL Down.
18-16RNSTSR/W0hReceiver Number Status for Margining Commands.
This field is reset upon DL Down.
15-8MRGPAYR/W9ChMargin Payload for Margining Commands.
This field is reset upon DL Down.
7R0R0hReserved
6USGMODR/W0hUsage Model for Margining Commands.
This field is reset upon DL Down.
5-3MRGTYPR/W7hMargin Type for Margining Commands.
This field is reset upon DL Down.
2-0RCVNUMR/W0hReceiver Number for Margining Commands.
This field is reset upon DL Down.

3.5.1.154 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG3 Register (Offset = 934h) [reset = 9C38h]

PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG3 is shown in Figure 12-1420 and described in Table 12-2778.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 3.

Table 12-2777 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0934h
Figure 12-1420 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG3 Register
3130292827262524
MPSTS
R/W-0h
2322212019181716
R1UMSTSMTSTSRNSTS
R-0hR/W-0hR/W-0hR/W-0h
15141312111098
MRGPAY
R/W-9Ch
76543210
R0USGMODMRGTYPRCVNUM
R-0hR/W-0hR/W-7hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2778 PCIE_CORE_PF0_I_MARGINING_LANE_CONTROL_STATUS_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31-24MPSTSR/W0hMargin Payload Status for Margining Commands.
This field is reset upon DL Down.
23R1R0hReserved
22UMSTSR/W0hUsage Model Status for Margining Commands.
This field is reset upon DL Down.
21-19MTSTSR/W0hMargin Type Status for Margining Commands.
This field is reset upon DL Down.
18-16RNSTSR/W0hReceiver Number Status for Margining Commands.
This field is reset upon DL Down.
15-8MRGPAYR/W9ChMargin Payload for Margining Commands.
This field is reset upon DL Down.
7R0R0hReserved
6USGMODR/W0hUsage Model for Margining Commands.
This field is reset upon DL Down.
5-3MRGTYPR/W7hMargin Type for Margining Commands.
This field is reset upon DL Down.
2-0RCVNUMR/W0hReceiver Number for Margining Commands.
This field is reset upon DL Down.

3.5.1.155 PCIE_CORE_PF0_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = 9C0h) [reset = A2010026h]

PCIE_CORE_PF0_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1421 and described in Table 12-2780.

Return to the Summary Table.

Physical Layer 16 GT/s Extended Capability Structure is used to configure the device for Gen4 Equalization and Gen4 Lane Error Reporting.

Table 12-2779 PCIE_CORE_PF0_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09C0h
Figure 12-1421 PCIE_CORE_PF0_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Register
31302928272625242322212019181716
PL16NXCAPPL16CAPVER
R/W-A20hR/W-1h
1514131211109876543210
PL16CAPID
R-26h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2780 PCIE_CORE_PF0_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20PL16NXCAPR/WA20hThe offset to the next PCI Extended Capability structure.
19-16PL16CAPVERR/W1hThis field is a PCI-SIG defined version number that indicates
the version of the Capability structure present.
15-0PL16CAPIDR26hIndicates that the associated extended capability structure is for
Physical layer 16 GT/s.
This field returns a Capability ID of 0026h.

3.5.1.156 PCIE_CORE_PF0_I_PL_16GTS_CAPABILITIES_REG Register (Offset = 9C4h) [reset = 0h]

PCIE_CORE_PF0_I_PL_16GTS_CAPABILITIES_REG is shown in Figure 12-1422 and described in Table 12-2782.

Return to the Summary Table.

Physical Layer 16GTs Capabilities Register.

Table 12-2781 PCIE_CORE_PF0_I_PL_16GTS_CAPABILITIES_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09C4h
Figure 12-1422 PCIE_CORE_PF0_I_PL_16GTS_CAPABILITIES_REG Register
313029282726252423222120191817161514131211109876543210
R0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2782 PCIE_CORE_PF0_I_PL_16GTS_CAPABILITIES_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R0R0hReserved

3.5.1.157 PCIE_CORE_PF0_I_PL_16GTS_CONTROL_REG Register (Offset = 9C8h) [reset = 0h]

PCIE_CORE_PF0_I_PL_16GTS_CONTROL_REG is shown in Figure 12-1423 and described in Table 12-2784.

Return to the Summary Table.

Physical Layer 16GTs Control Register.

Table 12-2783 PCIE_CORE_PF0_I_PL_16GTS_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09C8h
Figure 12-1423 PCIE_CORE_PF0_I_PL_16GTS_CONTROL_REG Register
313029282726252423222120191817161514131211109876543210
R0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2784 PCIE_CORE_PF0_I_PL_16GTS_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R0R0hReserved

3.5.1.158 PCIE_CORE_PF0_I_PL_16GTS_STATUS_REG Register (Offset = 9CCh) [reset = 0h]

PCIE_CORE_PF0_I_PL_16GTS_STATUS_REG is shown in Figure 12-1424 and described in Table 12-2786.

Return to the Summary Table.

Physical Layer 16GTs Status Register.

Table 12-2785 PCIE_CORE_PF0_I_PL_16GTS_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09CCh
Figure 12-1424 PCIE_CORE_PF0_I_PL_16GTS_STATUS_REG Register
3130292827262524
R0
R-0h
2322212019181716
R0
R-0h
15141312111098
R0
R-0h
76543210
R0LE16EP3S16EP2S16EP1S16EQC16
R-0hR/W-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2786 PCIE_CORE_PF0_I_PL_16GTS_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-5R0R0hReserved
4LE16R/W0hThis bit is set by Controller hardware to request the 16.0 GT/s Link equalization process to be performed on the Link.
Controller hardware sets this bit if a link equalization problem is detected at the end of equalization at 16GT/s.
Additionally, the Client Firmware may set this bit while requesting equalization through Local Management EP 16GTs Request Equalization Retrain Link bit.
This bit is cleared by writing a 1 to this bit position by the host, or writing a 0 from the LMI.
STICKY.
3EP3S16R0hThis bit, when set to 1, indicates that the Phase 3 of the Transmitter Equalization
procedure has completed successfully for 16.0 GT/s.
STICKY.
2EP2S16R0hThis bit, when set to 1, indicates that the Phase 2 of the Transmitter Equalization
procedure has completed successfully for 16.0 GT/s.
STICKY.
1EP1S16R0hThis bit, when set to 1, indicates that the Phase 1 of the Transmitter Equalization
procedure has completed successfully for 16.0 GT/s.
STICKY.
0EQC16R0hThis bit, when set to 1, indicates that the Transmitter Equalization procedure has
completed for 16.0 GT/s.
STICKY.

3.5.1.159 PCIE_CORE_PF0_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Register (Offset = 9D0h) [reset = 0h]

PCIE_CORE_PF0_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG is shown in Figure 12-1425 and described in Table 12-2788.

Return to the Summary Table.

Physical Layer 16GTs Local Data Parity Mismatch Status Register.

Table 12-2787 PCIE_CORE_PF0_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09D0h
Figure 12-1425 PCIE_CORE_PF0_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Register
3130292827262524
R0
R-0h
2322212019181716
R0
R-0h
15141312111098
R0
R-0h
76543210
R0LDPMS16
R-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2788 PCIE_CORE_PF0_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4R0R0hN/A
3-0LDPMS16R/W1C0hEach bit indicates if the corresponding Lane detected a Data Paritymismatch.
A value of 1b indicates that a mismatch was detected on the corresponding Lane Number.

3.5.1.160 PCIE_CORE_PF0_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register (Offset = 9D4h) [reset = 0h]

PCIE_CORE_PF0_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG is shown in Figure 12-1426 and described in Table 12-2790.

Return to the Summary Table.

Physical Layer 16GTs First Retimer Data Parity Mismatch Status Register.

Table 12-2789 PCIE_CORE_PF0_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09D4h
Figure 12-1426 PCIE_CORE_PF0_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register
3130292827262524
R0
R-0h
2322212019181716
R0
R-0h
15141312111098
R0
R-0h
76543210
R0FRDPMS16
R-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2790 PCIE_CORE_PF0_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4R0R0hN/A
3-0FRDPMS16R/W1C0hEach bit indicates if the first retimer in the corresponding Lane detected a Data Parity mismatch.
A value of 1b indicates that a mismatch was detected on the corresponding Lane Number.
The value of this field is undefined when no Retimers are present.

3.5.1.161 PCIE_CORE_PF0_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register (Offset = 9D8h) [reset = 0h]

PCIE_CORE_PF0_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG is shown in Figure 12-1427 and described in Table 12-2792.

Return to the Summary Table.

Physical Layer 16GTs Second Retimer Data Parity Mismatch Status Register.

Table 12-2791 PCIE_CORE_PF0_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09D8h
Figure 12-1427 PCIE_CORE_PF0_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register
3130292827262524
R0
R-0h
2322212019181716
R0
R-0h
15141312111098
R0
R-0h
76543210
R0SRDPMS16
R-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-2792 PCIE_CORE_PF0_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4R0R0hN/A
3-0SRDPMS16R/W1C0hEach bit indicates if the second retimer in the corresponding Lane detected a Data Parity mismatch.
A value of 1b indicates that a mismatch was detected on the corresponding Lane Number.
The value of this field is undefined when no Retimers are present.

3.5.1.162 PCIE_CORE_PF0_I_PL_16GTS_RESERVED_REG Register (Offset = 9DCh) [reset = 0h]

PCIE_CORE_PF0_I_PL_16GTS_RESERVED_REG is shown in Figure 12-1428 and described in Table 12-2794.

Return to the Summary Table.

Register at offset 1Ch in this capability is Reserved.

Table 12-2793 PCIE_CORE_PF0_I_PL_16GTS_RESERVED_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09DCh
Figure 12-1428 PCIE_CORE_PF0_I_PL_16GTS_RESERVED_REG Register
313029282726252423222120191817161514131211109876543210
R0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-2794 PCIE_CORE_PF0_I_PL_16GTS_RESERVED_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0R0R0hReserved

3.5.1.163 PCIE_CORE_PF0_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Register (Offset = 9E0h) [reset = FFFFFFFFh]

PCIE_CORE_PF0_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 is shown in Figure 12-1429 and described in Table 12-2796.

Return to the Summary Table.

This register contains the Upstream Port 16.0GT/s Transmitter Preset for
lanes 0, 1, 2 and 3, received from the Downstream Port during the 16GT/s Link Equalization procedure.

Table 12-2795 PCIE_CORE_PF0_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 09E0h
Figure 12-1429 PCIE_CORE_PF0_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Register
31302928272625242322212019181716
UPTP316DPTP316UPTP216DPTP216
R-FhR-FhR-FhR-Fh
1514131211109876543210
UPTP116DPTP116UPTP016DPTP016
R-FhR-FhR-FhR-Fh
LEGEND: R = Read Only; -n = value after reset
Table 12-2796 PCIE_CORE_PF0_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-28UPTP316RFh16.0GT/s Lane 3 Transmitter Preset value that the Downstream Port sends on the associated
Lane to the Endpoint device during 16GT/s Link Equalization.
27-24DPTP316RFhTransmitter Preset used for 16.0 GT/s equalization by this Port
when the Port is operating as a Downstream Port.
23-20UPTP216RFh16.0GT/s Lane 2 Transmitter Preset value that the Downstream Port sends on the associated
Lane to the Endpoint device during 16GT/s Link Equalization.
19-16DPTP216RFhTransmitter Preset used for 16.0 GT/s equalization by this Port
when the Port is operating as a Downstream Port.
15-12UPTP116RFh16.0GT/s Lane 1 Transmitter Preset value that the Downstream Port sends on the associated
Lane to the Endpoint device during 16GT/s Link Equalization.
11-8DPTP116RFhTransmitter Preset used for 16.0 GT/s equalization by this Port
when the Port is operating as a Downstream Port.
7-4UPTP016RFh16.0GT/s Lane 0 Transmitter Preset value that the Downstream Port sends on the associated
Lane to the Endpoint device during 16GT/s Link Equalization.
3-0DPTP016RFhTransmitter Preset used for 16.0 GT/s equalization by this Port
when the Port is operating as a Downstream Port.

3.5.1.164 PCIE_CORE_PF0_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = A20h) [reset = 0001001Fh]

PCIE_CORE_PF0_I_PTM_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1430 and described in Table 12-2798.

Return to the Summary Table.

Precision Time Measurement Extended Capability Structure is used discovering and controlling the distribution of a PTM hierarchy.

Table 12-2797 PCIE_CORE_PF0_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0A20h
Figure 12-1430 PCIE_CORE_PF0_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register
31302928272625242322212019181716
PTMNXCAPPTMCAPVER
R/W-0hR/W-1h
1514131211109876543210
PTMCAPID
R-1Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2798 PCIE_CORE_PF0_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20PTMNXCAPR/W0hThe offset to the next PCIe Extended Capability structure.
19-16PTMCAPVERR/W1hThis field is a PCI-SIG defined version number that indicates
the version of the Capability structure present.
15-0PTMCAPIDR1FhIndicates that the associated extended capability structure is for
Precision Time Measurement capability.
This field returns a Capability ID of 001Fh.

3.5.1.165 PCIE_CORE_PF0_I_PTM_CAPABILITIES_REG Register (Offset = A24h) [reset = 1h]

PCIE_CORE_PF0_I_PTM_CAPABILITIES_REG is shown in Figure 12-1431 and described in Table 12-2800.

Return to the Summary Table.

PTM Capabilities Register.

Table 12-2799 PCIE_CORE_PF0_I_PTM_CAPABILITIES_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0A24h
Figure 12-1431 PCIE_CORE_PF0_I_PTM_CAPABILITIES_REG Register
3130292827262524
R16
R-0h
2322212019181716
R16
R-0h
15141312111098
LOCCLKGR
R/W-0h
76543210
R3PTMRTCAPPTMRSCAPPTMRQCAP
R-0hR/W-0hR/W-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2800 PCIE_CORE_PF0_I_PTM_CAPABILITIES_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-8LOCCLKGRR/W0hThis field indicates the granularity of the PTM Local Clock in a PTM Time Source.
In EP Mode:
This field is not used and is set to 8'd00 by default.
Note: This bit must not be programmed in EP Mode.
7-3R3R0hReserved
2PTMRTCAPR/W0hThis bit is used to indicate that the Controller implements PTM Time Source Role and is capable of serving as PTM Root.
By default, this bit is set to 0 when the Controller is in Endpoint Mode.
Note: This bit must not be programmed in EP Mode.
1PTMRSCAPR/W0hThis bit is used to indicate support for PTM Responder Role.
By default, this bit is set to 0 when the Controller is in Endpoint Mode.
Note: This bit must not be programmed in EP Mode.
0PTMRQCAPR/W1hThis bit is used to indicate support for PTM Requester Role.
By default, this bit is set to 1 when the Controller is in Endpoint Mode.
This bit can be programmed through the local management APB interface if required.

3.5.1.166 PCIE_CORE_PF0_I_PTM_CONTROL_REG Register (Offset = A28h) [reset = 0h]

PCIE_CORE_PF0_I_PTM_CONTROL_REG is shown in Figure 12-1432 and described in Table 12-2802.

Return to the Summary Table.

PTM Control Register.

Table 12-2801 PCIE_CORE_PF0_I_PTM_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0A28h
Figure 12-1432 PCIE_CORE_PF0_I_PTM_CONTROL_REG Register
3130292827262524
R16
R-0h
2322212019181716
R16
R-0h
15141312111098
EFFGRN
R/W-0h
76543210
R2RTSELPTMEN
R-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-2802 PCIE_CORE_PF0_I_PTM_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-8EFFGRNR/W0hIn EP Mode:
This field provides information relating to the expected accuracy of the PTM Clock.
However, this field does not impact the functionality of the PTM Requester.
System SW is expected to program this field with to the value representing the maximum
Local Clock Granularity reported by the PTM Root and all the intervening PTM Time Sources.
7-2R2R0hReserved
1RTSELR/W0hSince Endpoint cannot be a PTM Root, this bit is set to 0 by default in Endpoint Mode.
Note: This bit must not be programmed in EP Mode.
0PTMENR/W0hWhen Set, this function is permitted to participate in the PTM mechanism as PTM
Requester.
By default, this bit is set to 0.
This field is configured by System SW.