The R5FSS has several master interfaces per core:
- 64-bit VBUSM master pair (1 read, 1 write) for L3 memory accesses; this is the main memory interface
- Includes region-based address translation (RAT)
- 32-bit VBUSM master pair (1 read, 1 write) for peripheral access
- Enabled at reset
- Supported for R5FSS0 ; not supported for MCU_R5FSS0
- 32-bit VBUSP master for peripheral access
- Includes logic that provides the R5F CPU with a private access to VIM and RAT
- Enabled at reset