SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-113 lists the memory-mapped registers for the INTR0_INTR_ROUTER_CFG registers. All register offset addresses not listed in Table 10-113 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
NAVSS0_INTR0_INTR_ROUTER_CFG | 310E 0000h |
MCU_NAVSS0_INTR0_CFG | 2854 0000h |
Offset | Acronym | Register Name | NAVSS0_INTR0_INTR_ROUTER_CFG Physical Address | MCU_NAVSS0_INTR0_CFG Physical Address |
---|---|---|---|---|
0h | INTR_ROUTER_PID | Interrupt router identification register | 310E 0000h | 2854 0000h |
4h + formula | INTR_ROUTER_MUXCNTL_y | Interrupt router mux control | 310E 0004h + formula | 2854 0004h + formula |
INTR_ROUTER_PID is shown in Figure 10-19 and described in Table 10-115.
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Identification register
Instance | Physical Address |
---|---|
NAVSS0_INTR0_INTR_ROUTER_CFG | 310E 0000h |
MCU_NAVSS0_INTR0_CFG | 2854 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNCTION | |||||||||||||
R-1h | R-2h | R-694h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJREV | CUSTOM | MINREV | ||||||||||||
R-10h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | PID scheme |
29-28 | BU | R | 2h | bu |
27-16 | FUNCTION | R | 694h | function |
15-11 | RTL | R | 10h | RTL version 10h - NAVSS0 Fh - MCU_NAVSS0 |
10-8 | MAJREV | R | 1h | major version |
7-6 | CUSTOM | R | 0h | custom id |
5-0 | MINREV | R | 0h | minor version |
INTR_ROUTER_MUXCNTL_y is shown in Figure 10-20 and described in Table 10-117.
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Interrupt mux control register
Offset = 4h + (y * 4); where y = 0h to 1FFh for NAVSS0
Offset = 4h + (y * 4); where y = 0h to 3Fh for MCU_NAVSS0
Instance | Physical Address |
---|---|
NAVSS0_INTR0_INTR_ROUTER_CFG | 310E 0004h + formula |
MCU_NAVSS0_INTR0_CFG | 2854 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | INT_ENABLE | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MUX_CONTROL | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MUX_CONTROL | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R/W | X | |
16 | INT_ENABLE | R/W | 0h | Interrupt output enable for interrupt y |
15-9 | RESERVED | R/W | X | |
8-0 | MUX_CONTROL | R/W | 0h | Mux control for interrupt y Avoid programming the mux control when input interrutps are enabled via INT_ENABLE. |