SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
IF: Is FIFO full? | MAILBOX_FIFO_STATUS_y[0] FULL | =0x1 |
Enable interrupt event | MAILBOX_IRQ_ENABLE_SET_j[1+ y*2] | 0x1 |
User (processor) can perform another task until interrupt occurs See Section 7.1.4.1.3.1 for interrupt handling in sending mode | ||
ELSE | ||
Write message | MAILBOX_MESSAGE_y[31:0] VALUE | 0x- |
ENDIF |