SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-1317 and Table 5-1318 show the programmable features for the POK modules based on the block diagrams shown in Figure 5-645 and Figure 5-646. Furthermore, each POK module has its own dedicated register to set its programmable features. Table 5-1319 lists those registers.
Programmable Feature | Bitfield in the POK Dedicated Register |
POK hysteresis enable | [31] HYST_EN |
POK over- or under-voltage detection mode | [7] OVER_VOLT_DET |
POK trim bits for voltage comparator threshold | [6-0] POK_TRIM |
Programmable Feature | Bitfield in the POK Dedicated Register |
POK hysteresis enable | [31] HYST_EN |
POK over- or under-voltage detection mode | [0] OVER_VOLT_DET |
PRG controls for the POKs include:
See the corresponding PRG control register in Table 5-1319.
POK and PRG | Voltage Monitored | Register(2) |
---|---|---|
PRG_PP_MAIN | CTRLMMR_WKUP_PRG_PP_MAIN_CTRL | |
IPOK_VDD_CORE | VDD_CORE | CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL |
IPOK_VDDR_CORE | VDDAR_CORE | CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL |
IPOK_VDD_CPU | VDD_CPU | CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL |
IPOK_VMON_EXT | VDDSHV in MCU | CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL |
IPOK_VMON_EXT_MAIN_1P8 | VDDSHV in MAIN | CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL |
IPOK_VMON_EXT_MAIN_3P3 | VDDSHV in MAIN | CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL |
PRG_PP_MCU | CTRLMMR_WKUP_PRG_PP_MCU_CTRL | |
IPOK_VDDR_MCU | VDDAR_MCU | CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL |
IPOK_VDDSHV_WKUP_GEN | VDDSHV0_MCU | CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL |
IPOK_CAP_VDDS_MCU_GEN | CAP_VDDS0_MCU | CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL |
PRG_PP_POR | CTRLMMR_WKUP_PRG_PP_POR_CTRL | |
IPOK_VDD_MCU_OV(1) | VDD_MCU | CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL |
IPOK_VDDA_PMIC_IN | PMIC VSYS | CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL |
PRG_PP_POR | CTRLMMR_WKUP_PRG_PP_POR_CTRL CTRLMMR_WKUP_PRG_PP_POR_STAT CTRLMMR_WKUP_POR_BANDGAP_CTRL |
|
POR_POKLVB_VDD_MCU_UV | VDD_MCU UV | CTRLMMR_WKUP_POR_POKHV_UV_CTRL |
POR_POKHV_VDDA_WKUP_POR_UV | VDDA_MCU (1.8V) UV | CTRLMMR_WKUP_POR_POKLVB_UV_CTRL |
POR_POKLVA_VDDA_WKUP_POR_OV | VDDA_MCU (1.8V) OV | CTRLMMR_WKUP_POR_POKLVA_OV_CTRL |
The possible values of the monitored voltage differ among the POK types, see Table 5-1315.
POK_TRIM [6:0] |
CORE_POK UV (OVER_VOLT _DET = 0) |
CORE_POK OV (OVER_VOLT _DET = 1) |
1P8_POK UV (OVER_VOLT _DET = 0) |
1P8_POK OV (OVER_VOLT _DET = 1) |
3P3_POK UV (OVER_VOLT _DET = 0) |
3P3_POK OV (OVER_VOLT _DET = 1) |
---|---|---|---|---|---|---|
0x00 | 0.475 V | 0.725 V | 1.425 V | 2.175 V | ||
0x01 | 0.4875 V | 0x7375 V | 1.4625 V | 2.2125 V | ||
0x02 | 0.50 V | 0.75 V | 1.5 V | 2.25 V | ||
… | ||||||
0xC | 1.432 V | |||||
0xD | 1.452 V | |||||
0xE | 1.473 V | |||||
… | ||||||
0x20 | 1.432 V | |||||
0x21 | 1.452 V | |||||
0x22 | 1.473 V | |||||
… | 0.475 V + POK_TRIM[7:0] *0.0125 V | 0.725 V + POK_TRIM[7:0] *0.0125 V | 0.7775 V + 0.02045* POK_TRIM[7:0] | 1.1865 V + 0.02045* POK_TRIM[7:0] | 1.425 V + POK_TRIM[7:0] *0.0375 V | 2.175 V + POK_TRIM[7:0] *0.0375 V |
0x2D | 3.8625 | |||||
0x2E | 2.127V | 3.9 | ||||
0x2F | 2.148 V | 3.9375 | ||||
0x30 | 2.168 V | |||||
… | ||||||
0x42 | 2.127 V | 3.9 V | ||||
0x43 | 2.148 V | 3.9375 V | ||||
0x44 | 1.325 V | 2.168 V | 3.975 V | |||
0x45 | 1.3375 V | |||||
0x46 | 1.35 V | |||||
… | ||||||
0x48 | 1.625 V | |||||
0x49 | 1.6375 V | |||||
0x4A | 1.65 V |
If the voltage values are programmable, they are set through [6-0] POK_TRIM bitfield in the corresponding POK control register, see Table 5-1319.