SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3816 lists the memory-mapped registers for the USB_ECC_AGGR_CFG registers. All register offset addresses not listed in Table 12-3816 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
USB0_ECC_AGGR | 02A1 3000h |
Offset | Acronym | Register Name | USB0_ECC_AGGR Physical Address |
---|---|---|---|
0h | USB_REV | Aggregator Revision Register | 02A1 3000h |
8h | USB_VECTOR | ECC Vector Register | 02A1 3008h |
Ch | USB_STAT | Misc Status | 02A1 300Ch |
10h + formula | USB_RESERVED_SVBUS_y | Reserved Area for Serial VBUS Registers | 02A1 3010h + formula |
3Ch | USB_SEC_EOI_REG | EOI Register | 02A1 303Ch |
40h | USB_SEC_STATUS_REG0 | Interrupt Status Register 0 | 02A1 3040h |
80h | USB_SEC_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 02A1 3080h |
C0h | USB_SEC_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 02A1 30C0h |
13Ch | USB_DED_EOI_REG | EOI Register | 02A1 313Ch |
140h | USB_DED_STATUS_REG0 | Interrupt Status Register 0 | 02A1 3140h |
180h | USB_DED_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 02A1 3180h |
1C0h | USB_DED_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 02A1 31C0h |
200h | USB_AGGR_ENABLE_SET | AGGR interrupt enable set Register | 02A1 3200h |
204h | USB_AGGR_ENABLE_CLR | AGGR interrupt enable clear Register | 02A1 3204h |
208h | USB_AGGR_STATUS_SET | AGGR interrupt status set Register | 02A1 3208h |
20Ch | USB_AGGR_STATUS_CLR | AGGR interrupt status clear Register | 02A1 320Ch |
USB_REV is shown in Figure 12-1927 and described in Table 12-3818.
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Revision parameters
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h |
Scheme |
29-28 | BU | R | 2h |
bu |
27-16 | MODULE_ID | R | 6A0h |
Module ID |
15-11 | REVRTL | R | 1Dh |
RTL version |
10-8 | REVMAJ | R | 2h |
Major version |
7-6 | CUSTOM | R | 0h |
Custom version |
5-0 | REVMIN | R | 0h |
Minor version |
USB_VECTOR is shown in Figure 12-1928 and described in Table 12-3820.
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ECC Vector Register
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3008h |
USB1_ECC_AGGR | 02A1 6008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R/W-X | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h |
Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h |
Read address |
15 | RD_SVBUS | R/W1S | 0h |
Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h |
Value written to select the corresponding ECC RAM for control or status |
USB_STAT is shown in Figure 12-1929 and described in Table 12-3822.
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Misc Status
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 300Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-X | R-1h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 1h |
Indicates the number of RAMS serviced by the ECC aggregator |
USB_RESERVED_SVBUS_y is shown in Figure 12-1930 and described in Table 12-3824.
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Offset = 10h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h |
Serial VBUS register data |
USB_SEC_EOI_REG is shown in Figure 12-1931 and described in Table 12-3826.
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EOI Register
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 303Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h |
EOI Register |
USB_SEC_STATUS_REG0 is shown in Figure 12-1932 and described in Table 12-3828.
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Interrupt Status Register 0
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMECC_PEND | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | RAMECC_PEND | R/W1S | 0h |
Interrupt Pending Status for ramecc_pend |
USB_SEC_ENABLE_SET_REG0 is shown in Figure 12-1933 and described in Table 12-3830.
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Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMECC_ENABLE_SET | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | RAMECC_ENABLE_SET | R/W1S | 0h |
Interrupt Enable Set Register for ramecc_pend |
USB_SEC_ENABLE_CLR_REG0 is shown in Figure 12-1934 and described in Table 12-3832.
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Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 30C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMECC_ENABLE_CLR | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | RAMECC_ENABLE_CLR | R/W1C | 0h |
Interrupt Enable Clear Register for ramecc_pend |
USB_DED_EOI_REG is shown in Figure 12-1935 and described in Table 12-3834.
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EOI Register
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 313Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h |
EOI Register |
USB_DED_STATUS_REG0 is shown in Figure 12-1936 and described in Table 12-3836.
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Interrupt Status Register 0
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMECC_PEND | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | RAMECC_PEND | R/W1S | 0h |
Interrupt Pending Status for ramecc_pend |
USB_DED_ENABLE_SET_REG0 is shown in Figure 12-1937 and described in Table 12-3838.
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Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMECC_ENABLE_SET | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | RAMECC_ENABLE_SET | R/W1S | 0h |
Interrupt Enable Set Register for ramecc_pend |
USB_DED_ENABLE_CLR_REG0 is shown in Figure 12-1938 and described in Table 12-3840.
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Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 31C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMECC_ENABLE_CLR | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | RAMECC_ENABLE_CLR | R/W1C | 0h |
Interrupt Enable Clear Register for ramecc_pend |
USB_AGGR_ENABLE_SET is shown in Figure 12-1939 and described in Table 12-3842.
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AGGR interrupt enable set Register
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h |
interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h |
interrupt enable set for parity errors |
USB_AGGR_ENABLE_CLR is shown in Figure 12-1940 and described in Table 12-3844.
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AGGR interrupt enable clear Register
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h |
interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h |
interrupt enable clear for parity errors |
USB_AGGR_STATUS_SET is shown in Figure 12-1941 and described in Table 12-3846.
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AGGR interrupt status set Register
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 3208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wincr | 0h |
interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h |
interrupt status set for parity errors |
USB_AGGR_STATUS_CLR is shown in Figure 12-1942 and described in Table 12-3848.
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AGGR interrupt status clear Register
Instance | Physical Address |
---|---|
USB0_ECC_AGGR | 02A1 320Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wdecr | 0h |
interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h |
interrupt status clear for parity errors |