SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 9-73 lists the memory-mapped registers for the MAIN2MCU_PLS_INTRTR0. All register offset addresses not listed in Table 9-73 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MAIN2MCU_PLS_INTRTR0_CFG | 00A2 0000h |
Offset | Acronym | Register Name | MAIN2MCU_PLS_ INTRTR0_CFG Physical Address |
---|---|---|---|
0h | MAIN2MCU_PLS_INTRTR0_PID | Peripheral identification register | 00A2 0000h |
4h + formula | MAIN2MCU_PLS_INTRTR0_MUXCNTL_n | Interrupt mux control register | 00A2 0004h + formula |
MAIN2MCU_PLS_INTRTR0_PID is shown in Figure 9-28 and described in Table 9-75.
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Peripheral identification register. Uniquely identifies the module and its specific revision.
Instance | Physical Address |
---|---|
MAIN2MCU_PLS_INTRTR0_CFG | 00A2 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66948100h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66948100h | TI internal data. Identifies revision of peripheral. |
MAIN2MCU_PLS_INTRTR0_MUXCNTL_n is shown in Figure 9-29 and described in Table 9-77.
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Interrupt mux control register.
Offset = 4h + (n * 4h); where n = 0h to 2Fh.
Instance | Physical Address |
---|---|
MAIN2MCU_PLS_INTRTR0_CFG | 00A2 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | INT_ENABLE | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16 | INT_ENABLE | R/W | 0h | Enable for interrupt output N |
15-7 | RESERVED | R | 0h | Reserved |
6-0 | ENABLE | R/W | 0h | Mux control for interrupt output N. Program this field according to Table 9-91. MAIN2MCU_PLS_INTRTR0 Interrupt Map. |