SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The timer can issue an overflow interrupt, a timer match interrupt, and a timer capture interrupt. Each internal interrupt source can be independently enabled and disabled in the interrupt-enable register (TIMER_IRQSTATUS_SET) and disabled in the interrupt-disable register (TIMER_IRQSTATUS_CLR). When the interrupt event is issued, the associated interrupt status bit is set in the timer status register (TIMER_IRQSTATUS).