SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 7-13 describes the events servicing in sending mode.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Read interrupt status bit | MAILBOX_IRQ_STATUS_CLR_j[1 + y*2] | 0x1 |
Write message | MAILBOX_MESSAGE_y[31:0] VALUE | 0x-- |
Write 1 to acknowledge interrupt | MAILBOX_IRQ_STATUS_CLR_j[1 + y*2] | 0x1 |