SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are two I2C modules integrated in the device MCU domain - MCU_I2C0 and MCU_I2C1. Figure 12-125 shows the integration of MCU_I2C0 and MCU_I2C1.
Table 12-237 through Table 12-239 summarize the integration of MCU_I2C[0-1] in device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCU_I2C0 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_I2C1 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_I2C0 | MCU_I2C0_OCP_CLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_I2C0 interface clock |
MCU_I2C0_SYS_CLK | MCU_PLL1_HSDIV3_CLKOUT | MCU_PLL1 | MCU_I2C0 functional clock | |
MCU_I2C1 | MCU_I2C1_OCP_CLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_I2C1 interface clock |
MCU_I2C1_SYS_CLK | MCU_PLL1_HSDIV3_CLKOUT | MCU_PLL1 | MCU_I2C1 functional clock | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_I2C0 | MCU_I2C0_RST | MOD_G_RST | LPSC0 | MCU_I2C0 reset |
MCU_I2C1 | MCU_I2C1_RST | MOD_G_RST | LPSC0 | MCU_I2C1 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_I2C0 | MCU_I2C0_CLKSTOP_WAKEUP_0 | WKUP_DMSC0_INTR_IN_55 | WKUP_DMSC0 | MCU_I2C0 wakeup interrupt. The interrupt is connected to DMSC0_WKUP, but instance is in an always on domain. See I2C Not Supported Features. | Pulse |
MCU_I2C0_POINTRPEND_0 | WKUP_DMSC0_INTR_IN_54 | WKUP_DMSC0 | MCU_I2C0 interrupt request | Level | |
GIC500_SPI_IN_884 | COMPUTE_CLUSTER0 | ||||
R5FSS0_CORE0_INTR_IN_462 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_462 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_23 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_23 | MCU_R5FSS0_CORE1 | ||||
MCU_I2C1 | MCU_I2C1_CLKSTOP_WAKEUP_0 | WKUP_DMSC0_INTR_IN_39 | WKUP_DMSC0 | MCU_I2C1 wakeup interrupt. The interrupt is connected to DMSC0_WKUP, but instance is in an always on domain. See I2C Not Supported Features. | Pulse |
MCU_I2C1_POINTRPEND_0 | WKUP_DMSC0_INTR_IN_38 | WKUP_DMSC0 | MCU_I2C1 interrupt request | Level | |
GIC500_SPI_IN_885 | COMPUTE_CLUSTER0 | ||||
R5FSS0_CORE0_INTR_IN_463 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_463 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_18 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_18 | MCU_R5FSS0_CORE1 |