SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There is one FSS integrated in the device MCU domain - MCU_FSS0. Figure 12-1958 shows the integration of MCU_FSS0.
Table 12-3878 through Table 12-3880 summarize the integration of MCU_FSS0 in the device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCU_FSS0 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_FSS0 | MCU_FSS0_ICLK | MCU_SYSCLK0/3 | WKUP_PLLCTRL0 | MCU_FSS0 Interface Clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_FSS0 | MCU_FSS0_RST | MOD_G_RST | LPSC0 | MCU_FSS0 System Reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_FSS0 | MCU_FSS0_MISC_0_ECC_INTR_ERR_PEND_0 | MCU_ESM0_LVL_IN_30 | MCU_ESM0 | MCU_FSS0 ECC Error Interrupt | Level |