SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-805 lists the PDMA PSI-L RX configuration registers (PDMA_PSILCFG_RX). These registers are not memory mapped and are accessed indirectly via CFG_PROXY modules in NAVSS.
Instance | Base Address |
---|---|
PDMA_PSILCFG_RX | N/A |
Offset | Acronym | Register Name | PDMA_PSILCFG_RX Physical Address |
---|---|---|---|
0h | PDMA_PSILCFG_RX_PEER_THREAD_ID | RX peer thread ID register | N/A |
1h | PDMA_PSILCFG_RX_PEER_CREDIT | RX peer credit register | N/A |
2h | PDMA_PSILCFG_RX_ENABLE | RX enable register | N/A |
400h | PDMA_PSILCFG_RX_STATIC_TR | RX static transfer request (X, Y) register | N/A |
401h | PDMA_PSILCFG_RX_STATIC_TR_Z | RX static transfer request (Z) register | N/A |
402h | PDMA_PSILCFG_RX_DEBUG_1 | RX debug/state register 1 | N/A |
403h | PDMA_PSILCFG_RX_DEBUG_2 | RX debug/state register 2 | N/A |
404h | PDMA_PSILCFG_RX_BYTE_COUNT | RX byte count register | N/A |
405h | PDMA_PSILCFG_RX_AASRC_RX_FIFO_CONFIG | RX AASRC Rx FIFO configuration register | N/A |
406h | PDMA_PSILCFG_RX_AASRC_RX_ORDER_TABLE0 | RX AASRC Rx order table 0 | N/A |
407h | PDMA_PSILCFG_RX_AASRC_RX_ORDER_TABLE1 | RX AASRC Rx order table 1 | N/A |
408h | PDMA_PSILCFG_RX_RT_ENABLE | RX real-time enable register | N/A |
40Fh | PDMA_PSILCFG_RX_DEBUG_3 | RX debug/state register 3 | N/A |
PDMA_PSILCFG_RX_PEER_THREAD_ID is shown in Figure 10-310 and described in Table 10-807.
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Peer Thread ID Register. This register contains the thread ID of the thread destination which is used for routing the messages. This register is only implemented for source threads.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
THREAD_PRIORITY | PEER_THREAD_WIDTH | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PEER_THREAD_ID | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_THREAD_ID | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | THREAD_PRIORITY | R | 0h | Priority level to use for this source thread in arbitration. This field is hard coded to 0h and is not writable |
28-24 | PEER_THREAD_WIDTH | R/W | 0h | Datapath width of paired peer destination thread. This field is encoded as follows: 0h = 32-bit 1h = 64-bit 2h = 128-bit 3h = 256-bit 4h = 512-bit |
23-16 | RESERVED | R | 0h | Reserved |
15-0 | PEER_THREAD_ID | R/W | 0h | Thread ID to which all nontransfer response, nonconfiguration messages from this thread are sent |
PDMA_PSILCFG_RX_PEER_CREDIT is shown in Figure 10-311 and described in Table 10-809.
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Peer Credit Register. This register contains a free credit count in completed destination data phases for the thread destination. This register is only implemented for source threads.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CREDIT_CNT | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | CREDIT_CNT | R/W | 0h | Free entries in destination thread. This field is encoded as follows: 0h to 80h = Actual count in data phases 81h to FFh = Reserved |
PDMA_PSILCFG_RX_ENABLE is shown in Figure 10-312 and described in Table 10-811.
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Enable Register. This register contains enable control for the thread.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE | R/W | 0h | When set, the RX channel is enabled. When cleared, the RX channel is disabled. When disabled, the channel ignores all credit returns, and will not generate egress data. A one-to-zero transition on this bit fully resets the channel. |
30-0 | RESERVED | R | 0h | Reserved |
PDMA_PSILCFG_RX_STATIC_TR is shown in Figure 10-313 and described in Table 10-813.
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Static Transfer Request (X, Y) Register. This register is used to define the 'X' and 'Y' parameters in a static TR.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BURST | ACC32 | RESERVED | X | ||||
R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | Y | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Y | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BURST | R/W | 0h | X-Y FIFO mode static TR: When set, enables VBUSP burst mode on this channel. See the XY burst description for more information. |
MCAN mode static TR: When set, enables VBUSP burst mode on this channel. See the MCAN burst description for more information. | ||||
AASRC mode static TR: Not used. | ||||
30 | ACC32 | R/W | 0h | X-Y FIFO mode static TR: When set, enables 32-bit access mode. On a 32-bit PDMA, all accesses will have XCNT=4 to support legacy IP that is not fully VBUSP compliant. This bit is ignored if the PDMA VBUSP port is not 32 bits wide. |
MCAN mode static TR: Not used. | ||||
AASRC mode static TR: When set, enables 32-bit access mode. On a 32-bit PDMA, all accesses will have XCNT=4 to support legacy IP that is not fully VBUSP compliant. This bit is ignored if the PDMA VBUSP port is not 32 bits wide. | ||||
29-27 | RESERVED | R | 0h | Reserved |
26-24 | X | R/W | 0h | X-Y FIFO mode static TR: Element size. This field specifies how much data is transferred in each write which is performed by the DMA. This field is encoded as follows: 0h = 8 bits; 1h =16 bits; 2h = 24 bits; 3h = 32 bits; 4h = 64 bits; 5h-7h = RESERVED. |
MCAN mode static TR: Not used. | ||||
AASRC mode static TR: Element size. This field specifies how much data is transferred in each write which is performed by the DMA. This field is encoded as follows: 0h = 8 bits; 1h =16 bits; 2h = 24 bits; 3h = 32 bits; 4h = 64 bits; 5h-7h = RESERVED. | ||||
23-12 | RESERVED | R | 0h | Reserved |
11-0 | Y | R/W | 0h | X-Y FIFO mode static TR: Element count. This field specifies how many elements to transfer each time a trigger is received on the channel. |
MCAN mode static TR: Buffer Size. This field specifies how many bytes should be read from an MCAN RX buffer. This field includes the 8 byte MCAN header on the initial packet fragment. A buffer size less than 16 is treated as 16, and a buffer size greater than 72 is treated as 72. | ||||
AASRC mode static TR: FIFO element count. In AASRC mode, a channel can service multiple FIFOs using a list supplied in its FIFO configuration. This field specifies how many times to service the FIFO list, hence how many elements to transfer from each FIFO, each time a trigger is received on the channel. Note for each loop specified by the value of Y, the entire list is processed. For example, if the FIFO list is 0, 1, 2, 3, and Y is set to 2 loops, the FIFOs are serviced in the order: 0, 1, 2, 3, 0, 1, 2, 3. |
PDMA_PSILCFG_RX_STATIC_TR_Z is shown in Figure 10-314 and described in Table 10-815.
Return to Summary Table.
Static Transfer Request (Z) Register. This register is used to define the 'Z' parameter in a static TR.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EOL | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | Z | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | EOL | R/W | 0h | EOL mode. Normally, when the Z count of FIFO operations has been reached, the PDMA will close the packet with an 'EOP' indication. When this flag is set, the PDMA will instead trigger an EOL at the completion of Z. |
30-12 | RESERVED | R | 0h | Reserved |
11-0 | Z | R/W | 0h | X-Y FIFO mode static TR: FIFO count. This field specifies how many full FIFO operations comprise a complete packet. When the count has been reached, the PDMA will close the packet with an EOP indication. If this parameter is set to NULL, then no packet delineation is supplied by the PDMA and all framing is controlled via the UDMA-P TR. |
MCAN mode static TR: Buffer Count. This field specifies how many MCAN RX buffers should be read before closing the CPPI packet with an EOP indication. When this count is greater than 1, multiple MCAN RX buffers will be read into a single CPPI packet buffer. The 8-byte MCAN header will be skipped on subsequent MCAN buffer reads. Setting this field to NULL will suppress all packet delineation, and should be avoided. | ||||
AASRC mode static TR: FIFO count. This field specifies how many full FIFO operations comprise a complete packet. When the count has been reached, the PDMA will close the packet with an EOP indication. If this parameter is set to NULL, then no packet delineation is supplied by the PDMA and all framing is controlled via the UDMA-P TR. |
PDMA_PSILCFG_RX_DEBUG_1 is shown in Figure 10-315 and described in Table 10-817.
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Debug/State Register 1. The debug/state registers give software applications additional information about the PDMA than they would need in regular opteration, but which may be useful in debug situations.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
Z | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Z | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Y | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Y | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | Z | R/W | 0h | This field holds the current Z count. In X-Y FIFO mode, this field holds the 1 based FIFO count of the FIFO being currently read, or the number of FIFO completions when the current operation completes. In MCAN mode, this field holds the zero based buffer index of the buffer currently being read, or the number of previously completed buffers. |
15-0 | Y | R/W | 0h | This field holds the current Y count. In X-Y FIFO mode, this is the number of X sized samples yet to be read from the peripheral for the DMA event being serviced. In MCAN mode, this field holds the next read offset to use when read to the CAN RX buffer. |
PDMA_PSILCFG_RX_DEBUG_2 is shown in Figure 10-316 and described in Table 10-819.
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Debug/State Register 2. The debug/state registers give software applications additional information about the PDMA than they would need in regular opteration, but which may be useful in debug situations.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INEVENT | TDOWN | PAUSE | SPACE | XSPACE | BUFFER | RESERVED | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STATE | EVENTCNT | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INEVENT | R/W | 0h | When set, the PDMA is in the middle of processing a FIFO event. |
30 | TDOWN | R/W | 0h | When set, the PDMA is processing a teardown operation. This bit is set simultaneously with the teardown bit in the source (RX) RT enable register. This bit will clear when the teardown is complete, regardless as to if the teardown bit in the pairing register is cleared or not. The teardown will propagate to the UDMA-P and its full completion status can be checked there. |
29 | PAUSE | R/W | 0h | When set, the PDMA is stopped in a paused state. This bit will clear if the channel is unpaused or disabled. |
28 | SPACE | R/W | 0h | When set, there is a non-zero amount of internal FIFO space available to hold new read data. |
27 | XSPACE | R/W | 0h | When set, there is enough internal FIFO space available to start servicing a peripheral DMA event. |
26 | BUFFER | R/W | 0h | This is the current RX buffer (0/1) for the current MCAN receive operation. |
25-24 | RESERVED | R | 0h | Reserved |
23-20 | STATE | R/W | 0h | This code reflects the current state of the PDMA channel, and is specific to the current implementation. |
19-16 | EVENTCNT | R/W | 0h | This field holds the number of backlogged DMA events yet to be serviced. |
15-0 | RESERVED | R | 0h | Reserved |
PDMA_PSILCFG_RX_BYTE_COUNT is shown in Figure 10-317 and described in Table 10-821.
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Byte Count Register. This register contains the number of bytes that have been written to the VBUSP mapped peripheral.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BYTES | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTES | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BYTES | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BYTES | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BYTES | R/W | 0h | This register contains the number of bytes that have been read from the VBUSP mapped peripheral. The register is write-to-decrement, so running counts can be tracked by reading register and then writing back the value that was read. It will wrap on overflow. It will reset to zero on a channel reset. |
PDMA_PSILCFG_RX_AASRC_RX_FIFO_CONFIG is shown in Figure 10-318 and described in Table 10-823.
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AASRC Rx FIFO configuration register.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
GROUPMODE | DMAREQRESET | RESERVED | |||||
R/W-0h | R/W-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
LASTSLOT | FIRSTSLOT | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMAREQMASK | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMAREQMASK | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | GROUPMODE | R/W | 0h | When set, the channel is in 'group mode'. It will look for group mode DMA requests, and access the group mode FIFOs. When clear, the channel is 'stream mode'. It will look for stream FIFO DMA requests, and access the stream mode FIFOs. |
30 | DMAREQRESET | R/W | 0h | When set, resets any latched DMA request using the DMAREQMASK. This bit is self-clearing. It should be used to synchronize the AASRC event status with the PDMA in the event that the AASRC has been previously used and it is not known if the PDMA may have latched, and is holding, previous DMA requests. |
29-24 | RESERVED | R | 0h | Reserved |
23-20 | LASTSLOT | R/W | 0h | This is the index (0-15) of the last slot in the RX FIFO ordering table used by this channel. The ordering table is read to get the FIFO index to access for each slot, starting with the first and ending with the last. |
19-16 | FIRSTSLOT | R/W | 0h | This is the index (0-15) of the first slot in the RX FIFO ordering table used by this channel. The ordering table is read to get the FIFO index to access for each slot, starting with the first and ending with the last. |
15-0 | DMAREQMASK | R/W | 0h | This field holds a set of flags indicating which AASRC DMA requests must fire in order for this channel to activate. In steam mode, these 16 flags correspond to the 16 DMA requests for each RX FIFO. The flags corresponding to all RX FIFOs involved with the channel should be set to 1. In group mode, these flags indicate which group mode DMA requests must fire. In this case, only bits [3:0] are relevant and only one bit should be set to 1 as a DMA channel only services a single group. |
PDMA_PSILCFG_RX_AASRC_RX_ORDER_TABLE0 is shown in Figure 10-319 and described in Table 10-825.
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AASRC RX order table 0 register.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENTRY7 | ENTRY6 | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ENTRY5 | ENTRY4 | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ENTRY3 | ENTRY2 | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENTRY1 | ENTRY0 | ||||||
R/W-0h | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | ENTRY7 | R/W | 7h | RX FIFO index for slot 7 |
27-24 | ENTRY6 | R/W | 6h | RX FIFO index for slot 6 |
23-20 | ENTRY5 | R/W | 5h | RX FIFO index for slot 5 |
19-16 | ENTRY4 | R/W | 4h | RX FIFO index for slot 4 |
15-12 | ENTRY3 | R/W | 3h | RX FIFO index for slot 3 |
11-8 | ENTRY2 | R/W | 2h | RX FIFO index for slot 2 |
7-4 | ENTRY1 | R/W | 1h | RX FIFO index for slot 1 |
3-0 | ENTRY0 | R/W | 0h | RX FIFO index for slot 0 |
PDMA_PSILCFG_RX_AASRC_RX_ORDER_TABLE1 is shown in Figure 10-320 and described in Table 10-827.
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AASRC RX order table 1 register.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENTRY15 | ENTRY14 | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ENTRY13 | ENTRY12 | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ENTRY11 | ENTRY10 | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENTRY9 | ENTRY8 | ||||||
R/W-0h | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | ENTRY15 | R/W | Fh | RX FIFO index for slot 15 |
27-24 | ENTRY14 | R/W | Eh | RX FIFO index for slot 14 |
23-20 | ENTRY13 | R/W | Dh | RX FIFO index for slot 13 |
19-16 | ENTRY12 | R/W | Ch | RX FIFO index for slot 12 |
15-12 | ENTRY11 | R/W | Bh | RX FIFO index for slot 11 |
11-8 | ENTRY10 | R/W | Ah | RX FIFO index for slot 10 |
7-4 | ENTRY9 | R/W | 9h | RX FIFO index for slot 9 |
3-0 | ENTRY8 | R/W | 8h | RX FIFO index for slot 8 |
PDMA_PSILCFG_RX_RT_ENABLE is shown in Figure 10-321 and described in Figure 10-321.
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Real Time Enable Register. This register allows enabling various channel settings in real time.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | TDOWN | PAUSE | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLE | FREE | |||||
R-0h | R-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE | R/W | 0h | When set, the RX channel is enabled. When cleared, the RX channel is disabled. When disabled, the channel ignores all DMA events from the peripheral. It maintains proper data transfers with the UDMA-P such that the credit handshake is not disrupted. However, unlike teardown, it does not close out the current open packet. Thus the TDOWN bit should always be used to disable an RX channel instead of manually clearing this bit. Failing to use teardown may result in stale data remaining in the internal RX FIFO, which would also prevent the channel from going idle without a channel reset. Note that this bit cannot be changed from 0 to 1 if the global enable bit in the peer enable register is 0. |
30 | TDOWN | R/W | 0h | When set, the channel will commence a RX channel teardown procedure. It will stop on the next FIFO boundary. It then clears the DMA event count and ignores all future DMA events from the peripheral. After stopping peripheral reads, the PDMA sends a teardown message to the UDMA-P that also closes the current packet with an EOP. If no packet is open at the time of the teardown, the message also includes SOP. The EOP teardown message may or may not contain final packet data. Once the channel teardown is complete and ready to be reused, the ENABLE bit is cleared. |
29 | PAUSE | R/W | 0h | When set, the channel is in a paused state. It will stop on the next FIFO boundary. It continues to accept and count DMA events from the peripherals but will not act on them. The PAUSE bit can be cleared and data will resume. Pause will not stop teardown from completing. |
28-2 | RESERVED | R | 0h | Reserved |
1 | IDLE | R | 0h | This is a read-only bit that signifies that the paused or disabled channel is also idle. It can only become set if PAUSE is set or ENABLE is cleared. |
0 | FREE | R/W | 0h | When cleared, the channel honors the debug suspend signal. When set, the channel will 'free run', regardless of the value of debug suspend. |
PDMA_PSILCFG_RX_DEBUG_3 is shown in Figure 10-322 and described in Table 10-831.
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Debug/State Register 3. The debug/state registers give software applications additional information about the PDMA than they would need in regular opteration, but which may be useful in debug situations.
Instance | Physical Address |
---|---|
PDMA_PSILCFG_RX | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
Z | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Z | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Z | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z | R/W | 0h | This field holds the full width value of the current Z count. In X-Y FIFO mode, this field holds the 1 based FIFO count of the FIFO being currently read, or the number of FIFO completions when the current operation completes. In MCAN mode, this field holds the zero based buffer index of the buffer currently being read, or the number of previously completed buffers. |