SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes the PCIe subsystem application fields from an environment point of view (external connections).
Table 12-2455 describes the SERDES signal names at device level related to PCIe subsystem and specifies their functions. For more information on the SERDES operation and interface signals, refer to Serializer/Deserializer (SerDes).
Device Level Signal | I/O(1) | Description |
---|---|---|
PCIE1 Subsystem | ||
PCIE1_RXN0 | I | PCIe Lane 0 Receive Differential Data (-) |
PCIE1_RXP0 | I | PCIe Lane 0 Receive Differential Data (+) |
PCIE1_TXN0 | O | PCIe Lane 0 Transmit Differential Data (-) |
PCIE1_TXP0 | O | PCIe Lane 0 Transmit Differential Data (+) |
PCIE1_RXN1 | I | PCIe Lane 1 Receive Differential Data (-) |
PCIE1_RXP1 | I | PCIe Lane 1 Receive Differential Data (+) |
PCIE1_TXN1 | O | PCIe Lane 1 Transmit Differential Data (-) |
PCIE1_TXP1 | O | PCIe Lane 1 Transmit Differential Data (+) |
PCIE1_RXN2 | I | PCIe Lane 2 Receive Differential Data (-) |
PCIE1_RXP2 | I | PCIe Lane 2 Receive Differential Data (+) |
PCIE1_TXN2 | O | PCIe Lane 2 Transmit Differential Data (-) |
PCIE1_TXP2 | O | PCIe Lane 2 Transmit Differential Data (+) |
PCIE1_RXN3 | I | PCIe Lane 3 Receive Differential Data (-) |
PCIE1_RXP3 | I | PCIe Lane 3 Receive Differential Data (+) |
PCIE1_TXN3 | O | PCIe Lane 3 Transmit Differential Data (-) |
PCIE1_TXP3 | O | PCIe Lane 3 Transmit Differential Data (+) |
PCIE1_CLKREQn | I/O | PCIe sideband signal for negotiation of L1 Substate entry/exit. The PCIE1_CLKREQn pin operates as an active low open-drain bidirection reference clock request pin. 1 = no request for clock; 0 = request for clock |
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.