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AM67A

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Arm®Cortex®-A53 4 TOPS Vision SoC mit RGB-IR ISP für 4 Kameras, Machine Vision, Robotik, Smart HMI

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AM67A

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Produktdetails

CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators CPU only, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS65224 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators CPU only, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS65224 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
FCBGA (AMW) 594 324 mm² 18 x 18

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 400MP/s operation
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-Time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 planned

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65 mm pitch with VCA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 400MP/s operation
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-Time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 planned

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65 mm pitch with VCA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

The AM67x scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM67x family is built for a broad set of cost-sensitive high performance compute applications in Factory Automation, Building Automation, and other markets.

The AM67x provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and MCU cores. All protected by industrial-grade security hardware accelerators.

AM67x contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The AM67x integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in AM67x to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM67x supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications.

The AM67x scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM67x family is built for a broad set of cost-sensitive high performance compute applications in Factory Automation, Building Automation, and other markets.

The AM67x provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and MCU cores. All protected by industrial-grade security hardware accelerators.

AM67x contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The AM67x integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in AM67x to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM67x supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet AM67x Processors datasheet (Rev. A) PDF | HTML 30 Sep 2024
* Errata J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Errata (Rev. A) PDF | HTML 15 Apr 2025
* User guide J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. C) PDF | HTML 25 Nov 2025
Application note Memory allocation for TIDL usage PDF | HTML 10 Nov 2025
Application note Optimizing TI Deep Learning Performance on C7xMMA Processors via Memory and DDR Bandwidth Reduction PDF | HTML 06 Nov 2025
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 05 Sep 2025
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 17 Jun 2025
Application note Building a Driver and Occupancy Monitoring System with an RGB-IR Camera (Rev. A) PDF | HTML 20 Mär 2025
User guide J722S/TDA4VEN/TDA4AEN/AM67 Power Estimation Tool User’s Guide (Rev. A) 03 Okt 2024
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 05 Aug 2024
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20 Jun 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 Jun 2024
Application note AM6xA ISP Tuning Guide (Rev. A) PDF | HTML 08 Mai 2024
Product overview J722S/AM67x/TDA4VEN/TDA4AEN Processor Automotive Power Designs using TPS6522312-Q1 PMIC PDF | HTML 18 Apr 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 Apr 2024
Application brief Top Five Design Considerations for Smart Multi-display Systems PDF | HTML 22 Mär 2024
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 Nov 2023
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 Nov 2023
Application note Building an Edge AI Application for Automated Retail Scanner on AM6xA MPUs PDF | HTML 17 Mai 2023
White paper Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A) PDF | HTML 13 Mär 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 Jan 2023
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 15 Aug 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 Apr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 Apr 2022
Technical article How to simplify your embedded edge AI application development PDF | HTML 28 Jan 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 Jan 2022
Application note TDA4 Flashing Techniques PDF | HTML 08 Jul 2021
White paper Sicherheitsaktivierung auf Jacinto™ 7-Prozessoren 04 Jan 2021
White paper Differenzierungsmöglichkeit durch MCU-Integration Prozessoren der Reihe Jacinto™ 22 Okt 2020
Application note OSPI Tuning Procedure PDF | HTML 08 Jul 2020

Design und Entwicklung

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Evaluierungsplatine

BEAGLEY-AI — BeagleBoard.org Foundation BeagleY®-AI Computer mit einer Platine, auf Basis von AM67A

Beagley® AI ist ein Open-Source-Einplatinencomputer, der entwickelt wurde, um den Prozess des Aufbaus intelligenter Mensch-Maschine-Schnittstellen (HMI) zu vereinfachen, indem er ein zuverlässiges eingebettetes System mit Kameras und Highspeed-Konnektivität ausstattet. Es verfügt über einen (...)

Von: BeagleBoard.org Foundation
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Evaluierungsplatine

EZURI-3P-CARBONAM67 — Ezurio CarbonAM67 SOM, OSM-MF-System auf Modul für AM67- und AM67A-Prozessoren

Ezurio ist ein führender Hersteller und Konnektivitätsexperte für drahtlose Module und System-on-Module. Die CarbonAM67 OSM-MF-Familie wird von der AM67x-Prozessorfamilie von Texas Instrument, dem TPS65224 PMIC von TI, unseren Sona Wi-Fi 6- und Bluetooth-Drahtlosmodulen angetrieben. Unsere (...)

Von: Ezurio
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Evaluierungsplatine

TQ-3P-SOM-TQMA67XX — TQMa67xx-System-on-Module von TQ-Group für AM67A- und AM67x-Arm-Cortex-A53-Prozessoren

Das Embedded-Modul TQMa67xx basiert auf der Prozessorfamilie AM67xx (Quad/Dual Cortex-A53). Das Modul ist so konzipiert, dass es alle pinkompatiblen Prozessoren innerhalb eines einzigen Platinenlayouts unterstützt. Der TQMa67xx eignet sich ideal für Anwendungen, die eine höhere Rechenleistung, (...)

Von: TQ-Group
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Debug-Tastkopf

TMDSEMU110-U — XDS110 JTAG-Debug-Tastkopf

Der XDS110 von Texas Instruments ist eine neue Klasse von Debug-Tastkopf (Emulator) für Embedded-Prozessoren von TI. Der XDS110 ersetzt die XDS100-Familie und unterstützt eine größere Anzahl von Standards (IEEE1149.1, IEEE1149.7, SWD) in einem einzigen Pod. Alle XDS-Debug-Tastköpfe unterstützen (...)

Benutzerhandbuch: PDF
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Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Der XDS200 ist ein Debug-Tastkopf (Emulator) zum Debugging von Embedded-Bausteinen von TI. Für die meisten Bausteine wird die Verwendung der neueren, kostengünstigeren XDS110 (www.ti.com/tool/TMDSEMU110-U) empfohlen. Der XDS200 unterstützt eine große Zahl von Standards (IEEE1149.1, IEEE1149.7, SWD) (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug-Tastkopf

LB-3P-TRACE32-ARM — Debug- und Trace-System Lauterbach TRACE32® für Arm®-basierte Mikrocontroller und Prozessoren

Die TRACE32®-Tools von Lauterbach sind eine Suite hochmoderner Hardware- und Softwarekomponenten, mit denen Entwickler alle Arten von Arm®-basierten Mikrocontrollern und Prozessoren analysieren, optimieren und zertifizieren können. Die weltweit anerkannten Debugging- und Trace-Lösungen für (...)

Von: Lauterbach GmbH
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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-ANDROID-AM67A — Processor SDK Android for AM67 and AM67A

The AM67A processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-AM67A — Processor SDK Linux for AM67A

The AM67A processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

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Anwendungssoftware und Frameworks

FIRMWARE-BUILDER-AM67A — Firmware builder for AM67A

The AM67A firmware builder® software development kits (SDKs) are used to update the firmware for edgeai SDKs
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Codebeispiel oder Demo

KDAB-3P-QT-DEMOS — Demo-Softwarebeispiel für die HMI der KDAB-Gruppe, geschrieben in Qt für AM6-Prozessoren

Die KDAB-Mehrfachbildschirm-Demo für Texas Instruments AM62 und AM62P zeigt die skalierbaren Grafik- und Anzeigefunktionen der AM623-, AM625- und AM62P-Prozessoren von TI. Diese Qt erstellte Demo zeigt das Rendern mehrerer Displays, die reibungslose UI-Leistung und hardwarebeschleunigte Grafik und (...)
Von: KDAB Group
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Erste Schritte

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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IDE, Konfiguration, Compiler oder Debugger

DDR-CONFIG-J722S — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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IDE, Konfiguration, Compiler oder Debugger

EDGE-AI-STUDIO — Edge AI Studio

Edge AI Studio is a collection of graphical and command line tools designed to accelerate edge AI development on TI processors, microcontrollers and radar sensors. Whether developing a proof of concept using a model from the TI Model Zoo or leveraging your own model, Edge AI Studio provides the (...)

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IDE, Konfiguration, Compiler oder Debugger

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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Betriebssystem (BS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Von: Green Hills Software
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Betriebssystem (BS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
Von: Green Hills Software
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Betriebssystem (BS)

TRZN-3P-TORIZON-OS — Einsatzbereite Industrial Embedded-Linux-Verteilung Torizon OS

Torizon OS ist ein kostenloses, quelloffenes Industrial Embedded-Linux-Betriebssystem, das auf die Vereinfachung der Entwicklung und Wartung von Produkten ausgelegt ist, die hohe Zuverlässigkeit und Sicherheit erfordern. Neben anderen zentralen Funktionen bietet es eine optimale Containerlaufzeit (...)
Von: Torizon
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Simulationsmodell

J722S BSDL Model

SPRM854.ZIP (12 KB) - BSDL Model
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Simulationsmodell

J722S IBIS Model

SPRM855.ZIP (4140 KB) - IBIS Model
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Simulationsmodell

J722S Thermal Model

SPRM856.ZIP (0 KB) - Thermal Model
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Gerberdatei

J722S/AM67x/TDA4VEN/TDA4AEN Evaluation Module Design Files (Rev. C)

SPRR495C.ZIP (556217 KB)
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCBGA (AMW) 594 Ultra Librarian
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