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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC3669

現行

具有 LVDS 介面和高達 32768x 降取的 16 位元、雙通道、500MSPS ADC

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產品規格表

ADC3669

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1400 Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 640 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12.3 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1400 Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 640 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12.3 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RTD) 64 81 mm² 9 x 9
  • 16-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -160.4dBFS/Hz
  • Thermal Noise: 76.4dBFS
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω and 200Ω termination
  • Input fullscale: 2VPP
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 75.6dBFS
    • SFDR HD2,3: 80dBc
    • SFDR worst spur: 94dBFS
  • INL: ±2 LSB (typical)
  • DNL: ±0.5 LSB (typical)
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR/Serial LVDS interface
    • 16-bit Parallel DDR LVDS for DDC bypass
    • Serial LVDS for decimation
    • 32-bit output option for high decimation
  • Power consumption: 300mW/channel (500MSPS)
  • 16-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -160.4dBFS/Hz
  • Thermal Noise: 76.4dBFS
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω and 200Ω termination
  • Input fullscale: 2VPP
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 75.6dBFS
    • SFDR HD2,3: 80dBc
    • SFDR worst spur: 94dBFS
  • INL: ±2 LSB (typical)
  • DNL: ±0.5 LSB (typical)
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR/Serial LVDS interface
    • 16-bit Parallel DDR LVDS for DDC bypass
    • Serial LVDS for decimation
    • 32-bit output option for high decimation
  • Power consumption: 300mW/channel (500MSPS)

The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).

The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).

The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. B) PDF | HTML 2025年 6月 5日
Application note Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 2025年 3月 28日
Application note Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 2025年 3月 26日
Application note Improving MSPS ADC’s SFDR While Relaxing AAF Requirements and Using Integrated DDC Features PDF | HTML 2025年 2月 18日
Application note The Fine Art of Passive Matching a High-Speed A/D Converter Analog Input Frontend PDF | HTML 2024年 12月 13日

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開發板

ADC3669EVM — ADC3669 評估模組

ADC3669EVM 是可用於評估 ADC3669 系列高速 ADC 的評估模組 (EVM)。ADC3669EVM 配備一個 ADC3669。ADC3669 是一款具有 LVDS 介面的 16 位元雙通道 ADC，執行取樣率高達 500MSPS。ADC3669EVM 可評估所有裝置速度等級和通道數量。
使用指南: PDF | HTML
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模擬型號

ADC3669 IBIS Model

SBAM516.ZIP (39 KB) - IBIS Model
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計算工具

ADC3669-NOISE-ANALYSIS-CALC — Noise analysis calculation tool (SNR/SFDR) for ADC3669 with amplifier input.

Calculation tool for analyzing noise of ADC3669 with an amplifier as the input network.
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設計工具

ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.

The ADC-TO-VREF-SELECT tool enables the pairing of TI analog-to-digital converters (ADCs) and series voltage references. Users can select an ADC device and the desired reference voltage, and the tool will list up to two voltage reference recommendations.
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