ADS7867
- Single 1.2-V to 3.6-V Supply Operation
- High Throughput
- 200/240/280KSPS for 12/10/8-Bit VDD
1.6 V - 100/120/140KSPS for 12/10/8-Bit VDD
1.2 V
- 200/240/280KSPS for 12/10/8-Bit VDD
- ±1.5LSB INL, 12-Bit NMC (ADS7866)
- 71 dB SNR, 83 dB THD at fIN = 30 kHz (ADS7866)
- Synchronized Conversion with SCLK
- SPI Compatible Serial Interface
- No Pipeline Delays
- Low Power
- 1.39 mW Typ at 200 KSPS, VDD = 3.6 V
- 0.39 mW Typ at 200 KSPS, VDD = 1.6 V
- 0.22 mW Typ at 100 KSPS, VDD = 1.2 V
- Auto Power-Down: 8 nA Typ, 300 nA Max
- 0 V to VDD Unipolar Input Range
- 6-Pin SOT-23 Package
- APPLICATIONS
- Battery Powered Systems
- Isolated Data Acquisition
- Medical Instruments
- Portable Communication
- Portable Data Acquisition Systems
- Automatic Test Equipment
The ADS7866/67/68 are low power, miniature, 12/10/8-bit A/D converters each with a unipolar, single-ended input. These devices can operate from a single 1.6 V to 3.6 V supply with a 200-KSPS throughput for ADS7866. In addition, these devices can maintain at least a 100-KSPS throughput with a supply as low as 1.2 V.
The sampling, conversion, and activation of digital output SDO are initiated on the falling edge of CS\. The serial clock SCLK is used for controlling the conversion rate and shifting data out of the converter. Furthermore, SCLK provides a mechanism to allow digital host processors to synchronize with the con- verter. These converters interface with micro-processors or DSPs through a high-speed SPI compatible serial interface. There are no pipeline delays associated with the device.
The minimum conversion time is determined by the frequency of the serial clock input, SCLK, while the maximum frequency of SCLK is determined by the minimum sampling time required to charge the input capacitance to 12/10/8-bit accuracy for the ADS7866/67/68, respectively. The maximum throughput is determined by how often a conversion is initiated when the minimum sampling time is met and the maximum SCLK frequency is used. Each device automatically powers down after each conversion, which allows each device to save power when the throughput is reduced while using the maximum SCLK frequency.
The converter reference is taken internally from the supply. Hence, the analog input range for these devices is 0 V to VDD.
These devices are available in a 6-pin SOT-23 package and are characterized over the industrial 40°C to 85°C temperature range.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 1.2-V 12/10/8-Bit 200-KSPS/100-KSPS MICRO-POWER MINIATURE ADC s/Serial Interface datasheet | 2005/7/1 | |||
| 電子書 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015/5/21 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011/3/17 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010/11/10 | ||||
| 應用說明 | Interfacing the ADS786x to TMS470 Processors | 2006/7/10 | ||||
| 應用說明 | Interfacing the ADS786x to the MSP430F2013 | 2006/6/15 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23 (DBV) | 6 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。