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類比轉數位轉換器 (ADC)
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ADS127L21

現行

具可編程 IIR 和 FIR 濾波器的 24 位元、512-kSPS 寬頻 Delta-Sigma ADC

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產品規格表

ADS127L21

現行
產品規格表 立即訂購

產品詳細資料

Resolution (Bits) 24 Sample rate (max) (ksps) 1365 Number of input channels 1 Interface type SPI Architecture Delta-Sigma Input type Differential, Single-ended Rating Catalog TI functional safety category Functional Safety-Capable Reference mode External Input voltage range (max) (V) 5 Input voltage range (min) (V) 0 Features Daisy-Chainable, Oscillator, Small Size, Wideband Operating temperature range (°C) -40 to 125 Analog supply voltage (min) (V) 2.85 Analog supply voltage (max) (V) 5.5 SNR (dB) 110 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
Resolution (Bits) 24 Sample rate (max) (ksps) 1365 Number of input channels 1 Interface type SPI Architecture Delta-Sigma Input type Differential, Single-ended Rating Catalog TI functional safety category Functional Safety-Capable Reference mode External Input voltage range (max) (V) 5 Input voltage range (min) (V) 0 Features Daisy-Chainable, Oscillator, Small Size, Wideband Operating temperature range (°C) -40 to 125 Analog supply voltage (min) (V) 2.85 Analog supply voltage (max) (V) 5.5 SNR (dB) 110 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
WQFN (RUK) 20 9 mm² (3 mm × 3 mm)
  • Programmable FIR filter
  • Programmable IIR filter
  • Wideband or low-latency filter modes
  • Programmable data rates:
    • Wideband filter: 512kSPS
    • Low-latency filter: 1.365MSPS
  • Conversion latency (low-latency filter): 3µs
  • AC accuracy with dc precision:
    • Dynamic range (200kSPS): 111.5dB (typical)
    • THD: –125dB (typical)
    • INL: 0.4ppm of FSR (typical)
    • Offset drift: 50nV/°C (typical)
    • Gain drift: 0.5ppm/°C (typical)
  • Power-scalable speed ranges:
    • Max speed: 512kSPS, 33mW (typical)
    • High speed: 400kSPS, 26mW (typical)
    • Mid speed: 200kSPS, 14mW (typical)
    • Low speed: 50kSPS, 4.3mW (typical)
  • Input range: ±VREF or ±2VREF
  • Buffered inputs
  • Internal or external clock operation
  • Functional Safety-Capable
  • Programmable FIR filter
  • Programmable IIR filter
  • Wideband or low-latency filter modes
  • Programmable data rates:
    • Wideband filter: 512kSPS
    • Low-latency filter: 1.365MSPS
  • Conversion latency (low-latency filter): 3µs
  • AC accuracy with dc precision:
    • Dynamic range (200kSPS): 111.5dB (typical)
    • THD: –125dB (typical)
    • INL: 0.4ppm of FSR (typical)
    • Offset drift: 50nV/°C (typical)
    • Gain drift: 0.5ppm/°C (typical)
  • Power-scalable speed ranges:
    • Max speed: 512kSPS, 33mW (typical)
    • High speed: 400kSPS, 26mW (typical)
    • Mid speed: 200kSPS, 14mW (typical)
    • Low speed: 50kSPS, 4.3mW (typical)
  • Input range: ±VREF or ±2VREF
  • Buffered inputs
  • Internal or external clock operation
  • Functional Safety-Capable

The ADS127L21 is a 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) featuring programmable digital filters. This digital filter has data rates up to 512kSPS using the wideband filter and up to 1365kSPS using the low-latency filter. The device offers an excellent combination of ac performance and dc precision with low power consumption.

Programmable infinite and finite impulse response (IIR and FIR) digital filters allow custom filter profiles, such as A-weighting compensation and frequency notch filters. The wideband or low-latency filter option optimize ac-signal performance or data throughput of dc signals, all in one device.

The low-drift modulator achieves excellent dc precision with low wideband noise for outstanding ac performance. The power-scalable architecture features four speed modes to optimize data rate, resolution, and power consumption. Signal and reference input buffers reduce driver loading for increased accuracy.

The serial interface features daisy-chain capability to reduce the number of signal lines over an isolation barrier. SPI input data and register memory contents are validated by cyclic-redundancy check (CRC) to enhance operational reliability.

The small 3mm × 3mm WQFN package is designed for space-limited applications. The device is fully specified for operation over the –40°C to +125°C temperature range.

The ADS127L21 is a 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) featuring programmable digital filters. This digital filter has data rates up to 512kSPS using the wideband filter and up to 1365kSPS using the low-latency filter. The device offers an excellent combination of ac performance and dc precision with low power consumption.

Programmable infinite and finite impulse response (IIR and FIR) digital filters allow custom filter profiles, such as A-weighting compensation and frequency notch filters. The wideband or low-latency filter option optimize ac-signal performance or data throughput of dc signals, all in one device.

The low-drift modulator achieves excellent dc precision with low wideband noise for outstanding ac performance. The power-scalable architecture features four speed modes to optimize data rate, resolution, and power consumption. Signal and reference input buffers reduce driver loading for increased accuracy.

The serial interface features daisy-chain capability to reduce the number of signal lines over an isolation barrier. SPI input data and register memory contents are validated by cyclic-redundancy check (CRC) to enhance operational reliability.

The small 3mm × 3mm WQFN package is designed for space-limited applications. The device is fully specified for operation over the –40°C to +125°C temperature range.
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針腳對針腳的功能與所比較的裝置相同。
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功能相同，但針腳輸出與所比較的裝置不同。
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ADS127L18 現行 八通道、同步取樣、512-kSPS、寬頻 24 位 Δ-Σ ADC Higher channel count (8), no programmable filters

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADS127L21 512kSPS, Programmable Filter, 24-Bit, Wideband Delta-Sigma ADC datasheet (Rev. C) PDF | HTML 2025/8/13
應用說明 A Simple, Java-Based CRC Calculator PDF | HTML 2026/3/4
應用說明 Design Considerations for Multiple Wide Bandwidth Delta- Sigma ADCs in Simultaneous-Sampling Systems (Rev. A) PDF | HTML 2025/12/29
應用說明 Anti-Alias Filter Design for a 100kHz Bandwidth Data Acquisition Signal Chain (Rev. A) PDF | HTML 2025/2/27
Application brief Using TI ADCs for Noise, Vibration, and Harshness Measurements PDF | HTML 2024/12/3
功能安全資訊 ADS1x7Lx1x Functional Safety FIT Rate, FMD and Pin FMA (Rev. C) PDF | HTML 2024/9/26
應用說明 Achieve High SNR with the PGA855, Fully Differential Programmable-Gain Amplifier PDF | HTML 2024/3/21
Application brief Benefits of Integrated FIR and IIR Filters in Delta-Sigma ADCs PDF | HTML 2023/5/11
應用說明 Four Channel Analog to Digital Interface with Sitara AM243x MCU+ PDF | HTML 2023/4/20
應用說明 Digital Filter Types in Delta-Sigma ADCs (Rev. A) PDF | HTML 2023/3/29

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADS127L21EVM-PDK — ADS127L21 評估模組，適用於具有易於驅動的輸入和寬頻或低延遲濾波器的 ADC

ADS127L21EVM-PDK 是用於 ADS127L21 24 位元高速自訂高頻寬濾波器 Delta-Sigma (ΔΣ) 類比轉數位轉換器 (ADC) 性能的評估平台。評估套件包含 ADS127L21EVM 電路板、PHI 控制器電路板，以及隨附的電腦軟體，其可讓使用者透過通用序列匯流排 (USB) 與 ADC 通訊、擷取資料，以及執行資料分析。
使用指南: PDF | HTML
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支援軟體

ADS127L21-C-EXAMPLE-CODE — ADS127L21 example C code

Expedite your embedded design using this example C code for the ADS127L21
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模擬型號

ADS127L21 IBIS Model

SBAM498.IBS (534 KB) - IBIS 模型
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計算工具

ADC-DESIGN-CALC — Online design calculator tool for TI Precision ADCs

ADC-DESIGN-CALC is an online resource with multiple ADC calculator tools (such as Digital Filter Response, Code-to-Voltage, CMR, CRC, etc.) for TI Precision ADCs.
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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設計工具

ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.

The ADC-TO-VREF-SELECT tool enables the pairing of TI analog-to-digital converters (ADCs) and series voltage references. Users can select an ADC device and the desired reference voltage, and the tool will list up to two voltage reference recommendations.
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參考設計

TIDA-010945 — 整合式低漂移精密數位萬用表和資料擷取訊號鏈參考設計

此參考設計說明用於 DC 量測之高性能訊號鏈的理論、設計與測試。主要目標應用是數位萬用表 (DMM)，但此設計也適用於其他應用，例如資料擷取 (DAQ) 和狀況監控。此設計使用高性能 24 位元類比轉數位轉換器 ADS127L21，以及低雜訊可編程增益放大器 PGA855，並具備 ±2.4ppm 的典型非線性與低溫度致漂移，進而實現高 DC 準確度。這些裝置皆高度整合，可簡化整體訊號鏈設計。

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WQFN (RUK) 20 Ultra Librarian
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