SBAC169 — ADS8332 EVM GUI Installer
支援產品和硬體
產品
精確 ADC
- ADS8332 — 具有 8 通道多工器和斷路器的 2.7V 至 5.5V 16 位元 500kSPS 低功耗序列 ADC
硬體開發
開發板
- ADS8332EVMV2-PDK — ADS8332 16 位元 500 kSPS 低功耗串聯 ADC 評估模組性能展示套件 (PDK)
The ADS8331 is a low-power, 16-bit, 500-k samples-per-second (SPS) analog-to-digital converter (ADC) with a unipolar, 4-to-1 multiplexer (mux) input. The device includes a 16-bit capacitor-based successive approximation register (SAR) ADC with inherent sample and hold.
The ADS8332 is based on the same core and includes a unipolar 8-to-1 input mux. Both devices offer a high-speed, wide-voltage serial interface and are capable of daisy-chain operation when multiple converters are used.
These converters are available in 24-pin, 4 × 4 QFN and 24-pin TSSOP packages and are fully specified for operation over the industrial –40°C to 85°C temperature range.
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ADS833x Low-Power, 16-Bit, 500-kSPS, 4- and 8-Channel Unipolar Input Analog-to-Digital Converters With Serial Interface datasheet (Rev. E) | PDF | HTML | 2016年 8月 9日 |
| White paper | Voltage-reference impact on total harmonic distortion | 2016年 8月 1日 | ||
| E-book | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015年 5月 21日 | ||
| Application note | Interfacing the ADS8332 to the TMS320F28335 DSP | 2012年 8月 20日 | ||
| User guide | ADS833xEVM User's Guide (Rev. A) | 2011年 5月 11日 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011年 3月 17日 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010年 11月 10日 |
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADS8332 評估模組 (EVM) 性能示範套件 (PDK) 是用於評估 ADS8332 漸近法暫存器 (SAR) 類比轉數位轉換器 (ADC) 性能的平台。ADS8332EVMV2-PDK 內含 ADS8332EVMV2 板、精密主機介面 (PHI) 控制器電路板,以及隨附的電腦軟體,可讓使用者透過通用序列匯流排 (USB) 與 ADC 通訊、擷取資料,以及執行資料分析。
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
| VQFN (RGE) | 24 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
Desktop software installer
General calculator tool for analog design support.
This is the first release of this tool.